From: Alex Lorenz Date: Thu, 9 Jul 2015 19:55:27 +0000 (+0000) Subject: MIR Serialization: Serialize the simple MachineFrameInfo attributes. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7c6ad33126df9ebbc66206b7882f336e6748202f;p=oota-llvm.git MIR Serialization: Serialize the simple MachineFrameInfo attributes. This commit serializes the 13 scalar boolean and integer attributes from the MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap, HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack, HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and HasMustTailInVarArgFunc. These attributes are serialized as part of the frameInfo YAML mapping, which itself is a part of the machine function's YAML mapping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/MIRYamlMapping.h b/include/llvm/CodeGen/MIRYamlMapping.h index 72b52586982..f7f64d10912 100644 --- a/include/llvm/CodeGen/MIRYamlMapping.h +++ b/include/llvm/CodeGen/MIRYamlMapping.h @@ -114,6 +114,52 @@ LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock) namespace llvm { namespace yaml { +/// Serializable representation of MachineFrameInfo. +/// +/// Doesn't serialize attributes like 'StackAlignment', 'IsStackRealignable' and +/// 'RealignOption' as they are determined by the target and LLVM function +/// attributes. +/// It also doesn't serialize attributes like 'NumFixedObject' and +/// 'HasVarSizedObjects' as they are determined by the frame objects themselves. +struct MachineFrameInfo { + // TODO: Serialize stack objects. + bool IsFrameAddressTaken = false; + bool IsReturnAddressTaken = false; + bool HasStackMap = false; + bool HasPatchPoint = false; + uint64_t StackSize = 0; + int OffsetAdjustment = 0; + unsigned MaxAlignment = 0; + bool AdjustsStack = false; + bool HasCalls = false; + // TODO: Serialize StackProtectorIdx and FunctionContextIdx + unsigned MaxCallFrameSize = 0; + // TODO: Serialize callee saved info. + // TODO: Serialize local frame objects. + bool HasOpaqueSPAdjustment = false; + bool HasVAStart = false; + bool HasMustTailInVarArgFunc = false; + // TODO: Serialize save and restore MBB references. +}; + +template <> struct MappingTraits { + static void mapping(IO &YamlIO, MachineFrameInfo &MFI) { + YamlIO.mapOptional("isFrameAddressTaken", MFI.IsFrameAddressTaken); + YamlIO.mapOptional("isReturnAddressTaken", MFI.IsReturnAddressTaken); + YamlIO.mapOptional("hasStackMap", MFI.HasStackMap); + YamlIO.mapOptional("hasPatchPoint", MFI.HasPatchPoint); + YamlIO.mapOptional("stackSize", MFI.StackSize); + YamlIO.mapOptional("offsetAdjustment", MFI.OffsetAdjustment); + YamlIO.mapOptional("maxAlignment", MFI.MaxAlignment); + YamlIO.mapOptional("adjustsStack", MFI.AdjustsStack); + YamlIO.mapOptional("hasCalls", MFI.HasCalls); + YamlIO.mapOptional("maxCallFrameSize", MFI.MaxCallFrameSize); + YamlIO.mapOptional("hasOpaqueSPAdjustment", MFI.HasOpaqueSPAdjustment); + YamlIO.mapOptional("hasVAStart", MFI.HasVAStart); + YamlIO.mapOptional("hasMustTailInVarArgFunc", MFI.HasMustTailInVarArgFunc); + } +}; + struct MachineFunction { StringRef Name; unsigned Alignment = 0; @@ -126,6 +172,8 @@ struct MachineFunction { // TODO: Serialize virtual register definitions. // TODO: Serialize the various register masks. // TODO: Serialize live in registers. + // Frame information + MachineFrameInfo FrameInfo; std::vector BasicBlocks; }; @@ -139,6 +187,7 @@ template <> struct MappingTraits { YamlIO.mapOptional("isSSA", MF.IsSSA); YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness); + YamlIO.mapOptional("frameInfo", MF.FrameInfo); YamlIO.mapOptional("body", MF.BasicBlocks); } }; diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp index fc1f9753309..e505ab4baeb 100644 --- a/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/lib/CodeGen/MIRParser/MIRParser.cpp @@ -21,6 +21,7 @@ #include "llvm/AsmParser/Parser.h" #include "llvm/AsmParser/SlotMapping.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/IR/BasicBlock.h" @@ -102,6 +103,9 @@ public: bool initializeRegisterInfo(MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF); + bool initializeFrameInfo(MachineFrameInfo &MFI, + const yaml::MachineFrameInfo &YamlMFI); + private: /// Return a MIR diagnostic converted from an MI string diagnostic. SMDiagnostic diagFromMIStringDiag(const SMDiagnostic &Error, @@ -245,6 +249,8 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { MF.setHasInlineAsm(YamlMF.HasInlineAsm); if (initializeRegisterInfo(MF.getRegInfo(), YamlMF)) return true; + if (initializeFrameInfo(*MF.getFrameInfo(), YamlMF.FrameInfo)) + return true; PerFunctionMIParsingState PFS; const auto &F = *MF.getFunction(); @@ -320,6 +326,25 @@ bool MIRParserImpl::initializeRegisterInfo( return false; } +bool MIRParserImpl::initializeFrameInfo(MachineFrameInfo &MFI, + const yaml::MachineFrameInfo &YamlMFI) { + MFI.setFrameAddressIsTaken(YamlMFI.IsFrameAddressTaken); + MFI.setReturnAddressIsTaken(YamlMFI.IsReturnAddressTaken); + MFI.setHasStackMap(YamlMFI.HasStackMap); + MFI.setHasPatchPoint(YamlMFI.HasPatchPoint); + MFI.setStackSize(YamlMFI.StackSize); + MFI.setOffsetAdjustment(YamlMFI.OffsetAdjustment); + if (YamlMFI.MaxAlignment) + MFI.ensureMaxAlignment(YamlMFI.MaxAlignment); + MFI.setAdjustsStack(YamlMFI.AdjustsStack); + MFI.setHasCalls(YamlMFI.HasCalls); + MFI.setMaxCallFrameSize(YamlMFI.MaxCallFrameSize); + MFI.setHasOpaqueSPAdjustment(YamlMFI.HasOpaqueSPAdjustment); + MFI.setHasVAStart(YamlMFI.HasVAStart); + MFI.setHasMustTailInVarArgFunc(YamlMFI.HasMustTailInVarArgFunc); + return false; +} + SMDiagnostic MIRParserImpl::diagFromMIStringDiag(const SMDiagnostic &Error, SMRange SourceRange) { assert(SourceRange.isValid() && "Invalid source range"); diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index d2e32ecd23f..b4e47232ec2 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -15,6 +15,7 @@ #include "MIRPrinter.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MIRYamlMapping.h" #include "llvm/IR/BasicBlock.h" @@ -42,6 +43,7 @@ public: void print(const MachineFunction &MF); void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo); + void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI); void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB); @@ -94,6 +96,7 @@ void MIRPrinter::print(const MachineFunction &MF) { YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); YamlMF.HasInlineAsm = MF.hasInlineAsm(); convert(YamlMF, MF.getRegInfo()); + convert(YamlMF.FrameInfo, *MF.getFrameInfo()); int I = 0; ModuleSlotTracker MST(MF.getFunction()->getParent()); @@ -120,6 +123,23 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled(); } +void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI, + const MachineFrameInfo &MFI) { + YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken(); + YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken(); + YamlMFI.HasStackMap = MFI.hasStackMap(); + YamlMFI.HasPatchPoint = MFI.hasPatchPoint(); + YamlMFI.StackSize = MFI.getStackSize(); + YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment(); + YamlMFI.MaxAlignment = MFI.getMaxAlignment(); + YamlMFI.AdjustsStack = MFI.adjustsStack(); + YamlMFI.HasCalls = MFI.hasCalls(); + YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize(); + YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment(); + YamlMFI.HasVAStart = MFI.hasVAStart(); + YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc(); +} + void MIRPrinter::convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB) { diff --git a/test/CodeGen/MIR/frame-info.mir b/test/CodeGen/MIR/frame-info.mir new file mode 100644 index 00000000000..c5468f94f33 --- /dev/null +++ b/test/CodeGen/MIR/frame-info.mir @@ -0,0 +1,91 @@ +# RUN: llc -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# This test ensures that the MIR parser parses machine frame info properties +# correctly. + +--- | + + define i32 @test(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + + define i32 @test2(i32 %a) { + entry: + %b = alloca i32 + store i32 %a, i32* %b + %c = load i32, i32* %b + ret i32 %c + } + +... +--- +name: test +isSSA: true +tracksRegLiveness: true + +# CHECK: frameInfo: +# CHECK-NEXT: isFrameAddressTaken: false +# CHECK-NEXT: isReturnAddressTaken: false +# CHECK-NEXT: hasStackMap: false +# CHECK-NEXT: hasPatchPoint: false +# CHECK-NEXT: stackSize: 0 +# CHECK-NEXT: offsetAdjustment: 0 +# Note: max alignment can be target specific when printed. +# CHECK-NEXT: maxAlignment: +# CHECK-NEXT: adjustsStack: false +# CHECK-NEXT: hasCalls: false +# CHECK-NEXT: maxCallFrameSize: 0 +# CHECK-NEXT: hasOpaqueSPAdjustment: false +# CHECK-NEXT: hasVAStart: false +# CHECK-NEXT: hasMustTailInVarArgFunc: false +# CHECK: body +frameInfo: + maxAlignment: 4 +body: + - id: 0 + name: entry +... +--- +name: test2 +isSSA: true +tracksRegLiveness: true + +# CHECK: test2 +# CHECK: frameInfo: +# CHECK-NEXT: isFrameAddressTaken: true +# CHECK-NEXT: isReturnAddressTaken: true +# CHECK-NEXT: hasStackMap: true +# CHECK-NEXT: hasPatchPoint: true +# CHECK-NEXT: stackSize: 4 +# CHECK-NEXT: offsetAdjustment: 4 +# Note: max alignment can be target specific when printed. +# CHECK-NEXT: maxAlignment: +# CHECK-NEXT: adjustsStack: true +# CHECK-NEXT: hasCalls: true +# CHECK-NEXT: maxCallFrameSize: 4 +# CHECK-NEXT: hasOpaqueSPAdjustment: true +# CHECK-NEXT: hasVAStart: true +# CHECK-NEXT: hasMustTailInVarArgFunc: true +# CHECK: body +frameInfo: + isFrameAddressTaken: true + isReturnAddressTaken: true + hasStackMap: true + hasPatchPoint: true + stackSize: 4 + offsetAdjustment: 4 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 4 + hasOpaqueSPAdjustment: true + hasVAStart: true + hasMustTailInVarArgFunc: true +body: + - id: 0 + name: entry +... +