From: Xing Zheng Date: Wed, 29 Jun 2016 02:36:08 +0000 (+0800) Subject: ARM: dts: rockchip: remove unused rk3228 dts files X-Git-Tag: firefly_0821_release~2354 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7d36af23c59af44b8a7a95f1559f92f569be29ef;p=firefly-linux-kernel-4.4.55.git ARM: dts: rockchip: remove unused rk3228 dts files There are old v3.10 dts and unsuitable for v4.4, we need to remove them. Change-Id: I070fb1fd5d513883f43dfbdab6f173e68fe48e72 Signed-off-by: Xing Zheng --- diff --git a/arch/arm/boot/dts/rk3228-clocks.dtsi b/arch/arm/boot/dts/rk3228-clocks.dtsi deleted file mode 100644 index e874a3f87a76..000000000000 --- a/arch/arm/boot/dts/rk3228-clocks.dtsi +++ /dev/null @@ -1,2162 +0,0 @@ -/* - * Copyright (C) 2014-2015 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include - -/{ - clocks { - compatible = "rockchip,rk-clocks"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x110e0000 0x1000>; - - fixed_rate_cons { - compatible = "rockchip,rk-fixed-rate-cons"; - - xin24m: xin24m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "xin24m"; - clock-frequency = <24000000>; - #clock-cells = <0>; - }; - - xin12m: xin12m { - compatible = "rockchip,rk-fixed-clock"; - clocks = <&xin24m>; - clock-output-names = "xin12m"; - clock-frequency = <12000000>; - #clock-cells = <0>; - }; - - hdmiphy_out: hdmiphy_out { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "hdmiphy_out"; - clock-frequency = <594000000>; - #clock-cells = <0>; - }; - - usbphy0_480m: usbphy0_480m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "usbphy0_480m"; - clock-frequency = <480000000>; - #clock-cells = <0>; - }; - - usbphy1_480m: usbphy1_480m { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "usbphy1_480m"; - clock-frequency = <480000000>; - #clock-cells = <0>; - }; - - jtag_clkin: jtag_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "jtag_clkin"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - dummy: dummy { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "dummy"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - gmac_clkin: gmac_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "gmac_clkin"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - phy_50m_out: phy_50m_out { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "phy_50m_out"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - phy_rx_out: phy_rx_out { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "phy_rx_out"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - phy_tx_out: phy_tx_out { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "phy_tx_out"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - clkin_hsadc_tsp: clkin_hsadc_tsp { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "clkin_hsadc_tsp"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - - i2s_clkin: i2s_clkin { - compatible = "rockchip,rk-fixed-clock"; - clock-output-names = "i2s_clkin"; - clock-frequency = <0>; - #clock-cells = <0>; - }; - }; - - fixed_factor_cons { - compatible = "rockchip,rk-fixed-factor-cons"; - - hclk_rkvdec: hclk_rkvdec { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&aclk_rkvdec>; - clock-output-names = "hclk_rkvdec"; - clock-div = <4>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - hclk_vpu: hclk_vpu { - compatible = "rockchip,rk-fixed-factor-clock"; - clocks = <&aclk_vpu>; - clock-output-names = "hclk_vpu"; - clock-div = <4>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - xin32k_out: xin32k_out { - compatible = "rockchip,rk-fixed-clock"; - clocks = <&clk_hdmi_cec>; - clock-output-names = "xin32k_out"; - clock-div = <1>; - clock-mult = <1>; - #clock-cells = <0>; - }; - - }; - - clock_regs { - compatible = "rockchip,rk-clock-regs"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0000 0x1000>; - ranges; - - /* PLL control regs */ - pll_cons { - compatible = "rockchip,rk-pll-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_apll: pll-clk@0000 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0000 0x10>; - mode-reg = <0x0040 0>; - status-reg = <0x04 10>; - clocks = <&xin24m>; - clock-output-names = "clk_apll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - clk_dpll: pll-clk@000c { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x000c 0x10>; - mode-reg = <0x0040 4>; - status-reg = <0x10 10>; - clocks = <&xin24m>; - clock-output-names = "clk_dpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - }; - - - clk_cpll: pll-clk@0018 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0018 0x10>; - mode-reg = <0x0040 8>; - status-reg = <0x1c 10>; - clocks = <&xin24m>; - clock-output-names = "clk_cpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_gpll: pll-clk@0024 { - compatible = "rockchip,rk3188-pll-clk"; - reg = <0x0024 0x10>; - mode-reg = <0x0040 12>; - status-reg = <0x28 10>; - clocks = <&xin24m>; - clock-output-names = "clk_gpll"; - rockchip,pll-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - /* Select control regs */ - clk_sel_cons { - compatible = "rockchip,rk-sel-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_sel_con0: sel-con@0044 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0044 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_core_div: clk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_core>; - clock-output-names = "clk_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - }; - - /* 5 reserved */ - - clk_core: clk_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&clk_apll>, <&clk_gpll>, <&clk_dpll>; - clock-output-names = "clk_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_bus: aclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_bus_mux>; - clock-output-names = "aclk_bus"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_bus_mux: aclk_bus_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; - clock-output-names = "aclk_bus"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15 reserved */ - - }; - - clk_sel_con1: sel-con@0048 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0048 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - pclk_dbg: pclk_dbg_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 4>; - clocks = <&clk_core>; - clock-output-names = "pclk_dbg"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_core: aclk_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <4 3>; - clocks = <&clk_core>; - clock-output-names = "aclk_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7 reserved */ - - hclk_bus: hclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_bus>; - clock-output-names = "hclk_bus"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 11:10 reserved */ - - pclk_bus: pclk_bus_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 3>; - clocks = <&aclk_bus>; - clock-output-names = "pclk_bus"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15 reserved */ - - }; - - clk_sel_con2: sel-con@004c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x004c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - hclk_vio: hclk_vio_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_iep>; - clock-output-names = "hclk_vio"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 7:5 reserved */ - - clk_nandc_div: clk_nandc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_nandc>; - clock-output-names = "clk_nandc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* 13: reserved */ - - clk_nandc: clk_nandc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_nandc"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15 reserved */ - - }; - - clk_sel_con3: sel-con@0050 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0050 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_i2s1_pll_div: clk_i2s1_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s1_pll>; - clock-output-names = "clk_i2s1_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 7: reserved */ - - clk_i2s1: clk_i2s1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_i2s1_pll_div>, <&i2s1_frac>, <&i2s_clkin>, <&xin12m>; - clock-output-names = "clk_i2s1"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 11:10: reserved */ - - clk_i2s1_out: clk_i2s1_out_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 1>; - clocks = <&clk_i2s1>, <&xin12m>; - clock-output-names = "i2s_clkout"; - #clock-cells = <0>; - }; - - /* 14:13: reserved */ - - clk_i2s1_pll: i2s1_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>,<&clk_gpll>; - clock-output-names = "clk_i2s1_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con4: sel-con@0054 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0054 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - testclk_div: testclk_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&testclk>; - clock-output-names = "testclk"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7:5 reserved */ - - clk_24m_div: clk_24m_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&xin24m>; - clock-output-names = "clk_24m"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 15:13 reserved */ - - }; - - clk_sel_con5: sel-con@0058 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0058 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_mac_pll_div: clk_mac_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_mac_pll>; - clock-output-names = "clk_mac_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_mac: clk_mac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 1>; - clocks = <&clk_mac_pll>, <&rmii_clkin>; - clock-output-names = "clk_mac"; - #clock-cells = <0>; - rockchip,flags = ; - #clock-init-cells = <1>; - }; - - /* 6 reserved */ - - clk_mac_pll: clk_mac_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <7 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_mac_pll"; - #clock-cells = <0>; - }; - - clk_gmac_div: clk_gmac_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_gmac>; - clock-output-names = "clk_gmac"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - /* 14:13 reserved */ - - clk_gmac: clk_gmac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_gmac"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con6: sel-con@005c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x005c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_div: spdif_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spdif_pll>; - clock-output-names = "clk_spdif_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 7 reserved */ - - clk_spdif: spdif_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>; - clock-output-names = "clk_spdif"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 14:10 reserved */ - - clk_spdif_pll: spdif_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>,<&clk_gpll>; - clock-output-names = "clk_spdif_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con7: sel-con@0060 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0060 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s1_frac: i2s1_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_i2s1_pll_div>; - clock-output-names = "i2s1_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con8: sel-con@0064 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0064 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s0_frac: i2s0_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_i2s0_pll_div>; - clock-output-names = "i2s0_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con9: sel-con@0068 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0068 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_i2s0_pll_div: clk_i2s0_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s0_pll>; - clock-output-names = "clk_i2s0_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 7: reserved */ - - clk_i2s0: clk_i2s0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_i2s0_pll_div>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>; - clock-output-names = "clk_i2s0"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 14:10: reserved */ - - clk_i2s0_pll: i2s0_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>,<&clk_gpll>; - clock-output-names = "clk_i2s0_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con10: sel-con@006c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x006c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_peri_div: aclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_peri>; - clock-output-names = "aclk_peri"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7:5: reserved */ - - hclk_peri: hclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 2>; - clocks = <&aclk_peri>; - clock-output-names = "hclk_peri"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - aclk_peri: aclk_peri_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; - clock-output-names = "aclk_peri"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - pclk_peri: pclk_peri_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <12 2>; - clocks = <&aclk_peri>; - clock-output-names = "pclk_peri"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x2 4 - 0x3 8>; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15: reserved */ - - }; - - clk_sel_con11: sel-con@0070 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0070 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdmmc0_div: clk_sdmmc0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 8>; - clocks = <&clk_sdmmc0>; - clock-output-names = "clk_sdmmc0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_sdmmc0: clk_sdmmc0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; - clock-output-names = "clk_sdmmc0"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_sdio: clk_sdio_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 2>; - clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; - clock-output-names = "clk_sdio"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_emmc: clk_emmc_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 2>; - clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>; - clock-output-names = "clk_emmc"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:14 reserved */ - - }; - - clk_sel_con12: sel-con@0074 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0074 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_sdio_div: clk_sdio_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 8>; - clocks = <&clk_sdio>; - clock-output-names = "clk_sdio"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - clk_emmc_div: clk_emmc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&clk_emmc>; - clock-output-names = "clk_emmc"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - }; - - }; - - clk_sel_con13: sel-con@0078 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0078 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart0_pll_div: clk_uart0_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart0_pll>; - clock-output-names = "clk_uart0_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* 7 reserved */ - - clk_uart0: clk_uart0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart0_pll_div>, <&uart0_frac>, <&xin24m>; - clock-output-names = "clk_uart0"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 11:10 reserved */ - - clk_uart0_pll: clk_uart0_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; - clock-output-names = "clk_uart0_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:14 reserved */ - - }; - - clk_sel_con14: sel-con@007c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x007c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart1_pll_div: clk_uart1_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart1_pll>; - clock-output-names = "clk_uart1_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* 7 reserved */ - - clk_uart1: clk_uart1_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart1_pll_div>, <&uart1_frac>, <&xin24m>; - clock-output-names = "clk_uart1"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 11:10 reserved */ - - clk_uart1_pll: clk_uart1_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; - clock-output-names = "clk_uart1_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:14 reserved */ - }; - - clk_sel_con15: sel-con@0080 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0080 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_uart2_pll_div: clk_uart2_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_uart2_pll>; - clock-output-names = "clk_uart2_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - }; - - /* 7 reserved */ - - clk_uart2: clk_uart2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_uart2_pll>, <&uart2_frac>, <&xin24m>; - clock-output-names = "clk_uart2"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 11:10 reserved */ - - clk_uart2_pll: clk_uart2_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; - clock-output-names = "clk_uart2_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:14 reserved */ - - }; - - clk_sel_con16: sel-con@0084 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0084 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s2_pll_div: i2s2_pll_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_i2s2_pll>; - clock-output-names = "clk_i2s2_pll"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 7: reserved */ - - clk_i2s2: clk_i2s2_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&i2s2_pll_div>, <&i2s2_frac>, <&i2s_clkin>, <&xin12m>; - clock-output-names = "clk_i2s2"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - rockchip,flags = ; - }; - - /* 14:10: reserved */ - - clk_i2s2_pll: i2s2_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>,<&clk_gpll>; - clock-output-names = "clk_i2s2_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con17: sel-con@0088 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0088 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart0_frac: uart0_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart0_pll_div>; - clock-output-names = "uart0_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con18: sel-con@008c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x008c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart1_frac: uart1_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart1_pll_div>; - clock-output-names = "uart1_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con19: sel-con@0090 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0090 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - uart2_frac: uart2_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&clk_uart2_pll_div>; - clock-output-names = "uart2_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con20: sel-con@0094 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0094 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - spdif_frac: spdif_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&spdif_div>; - clock-output-names = "spdif_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - - }; - - clk_sel_con21: sel-con@0098 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0098 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_hdmi_cec: clk_hdmi_cec_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 14>; - clocks = <&xin24m>; - clock-output-names = "clk_hdmi_cec"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - /* - clk_hdmi_cec_div: clk_hdmi_cec_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 14>; - clocks = <&clk_hdmi_cec>; - clock-output-names = "clk_hdmi_cec"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_hdmi_cec: clk_hdmi_cec_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&dummy>, <&dummy>, <&xin24m>; - clock-output-names = "clk_hdmi_cec"; - #clock-cells = <0>; - }; - */ - }; - - clk_sel_con22: sel-con@009c { - compatible = "rockchip,rk3188-selcon"; - reg = <0x009c 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_rga: clk_rga_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_rga>; - clock-output-names = "clk_rga"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7:0 reserved */ - - clk_tsp_div: clk_tsp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_tsp>; - clock-output-names = "clk_tsp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 14:13 reserved */ - - clk_tsp: clk_tsp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_tsp"; - #clock-cells = <0>; - }; - - }; - - clk_sel_con23: sel-con@00a0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_wifi_div: clk_wifi_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_wifi>; - clock-output-names = "clk_wifi"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_wifi: clk_wifi_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>; - clock-output-names = "clk_wifi"; - #clock-cells = <0>; - }; - - /* 7 reserved */ - - clk_hdcp_div: clk_hdcp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 6>; - clocks = <&clk_hdcp>; - clock-output-names = "clk_hdcp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_hdcp: clk_hdcp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>; - clock-output-names = "clk_hdcp"; - #clock-cells = <0>; - }; - - }; - - clk_sel_con24: sel-con@00a4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_crypto_div: clk_crypto_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_crypto>; - clock-output-names = "clk_crypto"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_crypto: clk_crypto_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_crypto"; - #clock-cells = <0>; - }; - - clk_tsadc: clk_tsadc_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <6 10>; - clocks = <&xin24m>; - clock-output-names = "clk_tsadc"; - rockchip,div-type = ; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - }; - - clk_sel_con25: sel-con@00a8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00a8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_spi0_div: clk_spi0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 7>; - clocks = <&clk_spi0>; - clock-output-names = "clk_spi0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7 reserved */ - - clk_spi0: clk_spi0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 1>; - clocks = <&clk_cpll>, <&clk_gpll>; - clock-output-names = "clk_spi0"; - #clock-cells = <0>; - }; - - /* 15:9 reserved */ - - }; - - clk_sel_con26: sel-con@00ac { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00ac 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_ddr_div: clk_ddr_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 2>; - clocks = <&clk_ddr>; - clock-output-names = "clk_ddr"; - rockchip,div-type = ; - rockchip,div-relations = - <0x0 1 - 0x1 2 - 0x3 4>; - #clock-cells = <0>; - rockchip,flags = <(CLK_GET_RATE_NOCACHE | - CLK_SET_RATE_NO_REPARENT)>; - rockchip,clkops-idx = ; - }; - - /* 7:2 reserved */ - - clk_ddr: clk_ddr_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 2>; - clocks = <&clk_dpll>, <&clk_gpll>, <&clk_apll>; - clock-output-names = "clk_ddr"; - #clock-cells = <0>; - }; - - /* 15:10 reserved */ - - }; - - clk_sel_con27: sel-con@00b0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_vop0_pll: dclk_vop0_pll_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <0 1>; - clocks = <&clk_gpll>, <&clk_cpll>; - clock-output-names = "dclk_vop0_pll"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - dclk_vop0: dclk_vop0_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <1 1>; - clocks = <&hdmi_phy_clk>, <&dummy>;/*dclk_vop0_div*/ - clock-output-names = "dclk_vop0"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 7:2 reserved */ - - dclk_vop0_div: dclk_vop0_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 8>; - clocks = <&dclk_vop0_pll>; - clock-output-names = "dclk_vop0"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - }; - - clk_sel_con28: sel-con@00b4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_rkvdec_div: aclk_rkvdec_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_rkvdec>; - clock-output-names = "aclk_rkvdec"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 5 reserved */ - - aclk_rkvdec: aclk_rkvdec_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <6 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_rkvdec"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - clk_vdec_cabac_div: clk_vdec_cabac_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_vdec_cabac>; - clock-output-names = "clk_vdec_cabac"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 13 reserved */ - - clk_vdec_cabac: clk_vdec_cabac_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "clk_vdec_cabac"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - }; - - clk_sel_con29: sel-con@00b8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00b8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - dclk_hdmiphy_div: dclk_hdmiphy_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 3>; - clocks = <&dclk_vop0_pll>; - clock-output-names = "dclk_hdmiphy"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - /* 7:3 reserved */ - - clk_macphy_div: clk_macphy_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 3>; - clocks = <&clk_macphy>; - clock-output-names = "clk_macphy"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - rmii_clkin: rmii_clkin { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <10 1>; - clocks = <&gmac_clkin>, <&phy_50m_out>; - clock-output-names = "rmii_clkin"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - /* - clk_mac_tx: clk_mac_tx { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <11 1>; - clocks = <&clk_gates5 6>, <&phy_tx_out>; - clock-output-names = "clk_mac_tx"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - */ - clk_macphy: clk_macphy_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <12 1>; - clocks = <&clk_mac_pll_div>, <&gmac_clkin>; - clock-output-names = "clk_macphy"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:13 reserved */ - - }; - - clk_sel_con30: sel-con@00bc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00bc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - i2s2_frac: i2s2_frac { - compatible = "rockchip,rk3188-frac-con"; - clocks = <&i2s2_pll_div>; - clock-output-names = "i2s2_frac"; - /* numerator denominator */ - rockchip,bits = <0 32>; - rockchip,clkops-idx = - ; - #clock-cells = <0>; - }; - }; - - clk_sel_con31: sel-con@00c0 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c0 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_iep_div: aclk_iep_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_iep>; - clock-output-names = "aclk_iep"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_iep: aclk_iep_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_iep"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 7: reserved */ - - aclk_hdcp_div: aclk_hdcp_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_hdcp>; - clock-output-names = "aclk_hdcp"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_hdcp: aclk_hdcp_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_hdcp"; - #clock-cells = <0>; - }; - - /* 15: reserved */ - }; - - clk_sel_con32: sel-con@00c4 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c4 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_vpu_div: aclk_vpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_vpu>; - clock-output-names = "aclk_vpu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_vpu: aclk_vpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_vpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15:7 reserved */ - - }; - - clk_sel_con33: sel-con@00c8 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00c8 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - aclk_vop_div: aclk_vop_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&aclk_vop>; - clock-output-names = "aclk_vop"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_vop: aclk_vop_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_vop"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 7 reserved */ - - aclk_rga_div: aclk_rga_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&aclk_rga>; - clock-output-names = "aclk_rga"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - aclk_rga: aclk_rga_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "aclk_rga"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 15 reserved */ - - }; - - clk_sel_con34: sel-con@00cc { - compatible = "rockchip,rk3188-selcon"; - reg = <0x00cc 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - clk_gpu_div: clk_gpu_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <0 5>; - clocks = <&clk_gpu>; - clock-output-names = "clk_gpu"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_gpu: clk_gpu_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <5 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "clk_gpu"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 7 reserved */ - - clk_vdec_core_div: clk_vdec_core_div { - compatible = "rockchip,rk3188-div-con"; - rockchip,bits = <8 5>; - clocks = <&clk_vdec_core>; - clock-output-names = "clk_vdec_core"; - rockchip,div-type = ; - #clock-cells = <0>; - rockchip,clkops-idx = ; - }; - - clk_vdec_core: clk_vdec_core_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 2>; - clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>; - clock-output-names = "clk_vdec_core"; - #clock-cells = <0>; - #clock-init-cells = <1>; - - }; - - /* 15 reserved */ - }; - - clk_sel_con35: sel-con@0134 { - compatible = "rockchip,rk3188-selcon"; - reg = <0x0134 0x4>; - #address-cells = <1>; - #size-cells = <1>; - - /* 7:0 reserved */ - - testclk: testclk_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <8 4>; - clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&clk_gpu>, <&aclk_peri>, <&aclk_core>; - clock-output-names = "testclk"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - /* 12 reserved */ - - hdmi_phy_clk: hdmi_phy_clk_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <13 1>; - clocks = <&hdmiphy_out>, <&xin24m>; - clock-output-names = "hdmi_phy_clk"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - usb480m_phy: usb480m_phy_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <14 1>; - clocks = <&usbphy0_480m>, <&usbphy1_480m>; - clock-output-names = "usb480m_phy"; - #clock-cells = <0>; - #clock-init-cells = <1>; - }; - - usb480m: usb480m_mux { - compatible = "rockchip,rk3188-mux-con"; - rockchip,bits = <15 1>; - clocks = <&usb480m_phy>, <&xin24m>; - clock-output-names = "usb480m"; - #clock-cells = <0>; - rockchip,clkops-idx = - ; - #clock-init-cells = <1>; - }; - }; - }; - /* Gate control regs */ - clk_gate_cons { - compatible = "rockchip,rk-gate-cons"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clk_gates0: gate-clk@00d0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d0 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dummy>, <&clk_i2s0_pll>, - - <&i2s0_frac>, <&clk_i2s0>, - <&dummy>, <&clk_i2s2_pll>, - - <&i2s2_frac>, <&clk_i2s2>, - <&clk_i2s1_pll>, <&i2s1_frac>, - - <&dummy>, <&clk_i2s1_out>, - <&clk_i2s1>, <&testclk>; - - clock-output-names = - "reserved", "reserved", - "reserved", "clk_i2s0_pll", - - "i2s0_frac", "i2s0_8ch", - "reserved", "clk_i2s2_pll", - - "i2s2_frac", "i2s2_2ch", - "clk_i2s1_pll", "i2s1_frac", - - "reserved", "i2s_clkout", - "i2s1_8ch", "testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@00d4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d4 0x4>; - clocks = - <&clk_nandc>, <&aclk_vop>, - <&aclk_rga>, <&jtag_clkin>, - - <&aclk_hdcp>, <&xin24m>, - <&xin24m>, <&clk_mac_pll>, - - <&clk_uart0_pll>, <&uart0_frac>, - <&clk_uart1_pll>, <&uart1_frac>, - - <&clk_uart2_pll>, <&uart2_frac>, - <&dummy>, <&dummy>; - - clock-output-names = - "clk_nandc", "aclk_vop", - "aclk_rga", "clk_jtag", - - "aclk_hdcp", "clk_otgphy0", - "clk_otgphy1", "clk_mac_pll", - - "clk_uart0_pll", "uart0_frac", - "clk_uart1_pll", "uart1_frac", - - "clk_uart2_pll", "uart2_frac", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates2: gate-clk@00d8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00d8 0x4>; - clocks = - <&dummy>, <&dummy>, - <&clk_gmac>, <&dummy>, - - <&dummy>, <&dummy>, - <&clk_tsp>, <&clk_crypto>, - - <&clk_tsadc>, <&clk_spi0>, - <&clk_spdif_pll>, <&clk_sdmmc0>, - - <&spdif_frac>, <&clk_sdio>, - <&clk_emmc>, <&clk_wifi>; - - clock-output-names = - "reserved", "clk_ddrmon", - "clk_gmac", "reserved", - - "reserved", "reserved", - "clk_tsp", "clk_crypto", - - "clk_tsadc", "clk_spi0", - "clk_spdif_pll", "clk_sdmmc0", - - "spdif_frac", "clk_sdio", - "clk_emmc", "clk_wifi"; - - #clock-cells = <1>; - }; - - clk_gates3: gate-clk@00dc { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00dc 0x4>; - clocks = - <&aclk_iep>, <&dummy>, - <&aclk_rkvdec>, <&clk_vdec_cabac>, - - <&clk_vdec_core>, <&clk_hdcp>, - <&aclk_rga>, <&xin24m>, - - <&clk_hdmi_cec>, <&dummy>, - <&dummy>, <&aclk_vpu>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "aclk_iep", "dclk_vop0", - "aclk_rkvdec", "clk_vdec_cabac", - - "clk_vdec_core", "clk_hdcp", - "clk_rga", "clk_hdmi_hdcp", - - "clk_hdmi_cec", "reserved", - "reserved", "aclk_vpu", - - "reserved", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates4: gate-clk@00e0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e0 0x4>; - clocks = - <&clk_core>, <&clk_core>, - <&aclk_core>, <&dummy>, - - <&aclk_vpu>, <&aclk_rkvdec>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "aclk_core", "pclk_dbg", - "aclk_gic400", "reserved", - - "hclk_vpu", "hclk_rkvdec", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates5: gate-clk@00e4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e4 0x4>; - clocks = - <&aclk_peri>, <&aclk_peri>, - <&aclk_peri>, <&clk_mac>, - - <&clk_mac>, <&clk_mac>, - <&clk_mac>, <&clk_macphy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "aclk_peri", "hclk_peri", - "pclk_peri", "clk_mac_ref", - - "clk_mac_refout", "clk_mac_rx", - "clk_mac_tx", "clk_macphy", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates6: gate-clk@00e8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00e8 0x4>; - clocks = - <&aclk_bus>, <&aclk_bus>, - <&aclk_bus>, <&pclk_bus>, - - <&pclk_bus>, <&xin24m>, - <&xin24m>, <&xin24m>, - - <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - - <&dummy>, <&pclk_bus>, - <&dummy>, <&dummy>; - - clock-output-names = - "aclk_bus", "hclk_bus", - "pclk_bus", "pclk_bus_pre", - - "pclk_phy", "clk_timer0", - "clk_timer1", "clk_timer2", - - "clk_timer3", "clk_timer4", - "clk_timer5", "reserved", - - "reserved", "pclk_ddr", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates7: gate-clk@00ec { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00ec 0x4>; - clocks = - <&clk_ddr_div>, <&clk_ddr_div>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&clk_gpu>, <&clk_gpu>; - - clock-output-names = - "clk_ddrphy", "clk4x_ddrphy", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "g_aclk_gpu", "g_aclk_gpu_noc"; - - #clock-cells = <1>; - }; - - clk_gates8: gate-clk@00f0 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f0 0x4>; - clocks = - <&aclk_bus>, <&aclk_bus>, - <&aclk_bus>, <&hclk_bus>, - - <&clk_gates6 13>, <&clk_gates7 0>, - <&clk_gates6 13>, <&hclk_bus>, - - <&hclk_bus>, <&hclk_bus>, - <&hclk_bus>, <&hclk_bus>, - - <&hclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>; - - clock-output-names = - "g_aclk_intmem", "g_intmem_mbist", - "g_aclk_dmac_bus", "g_hclk_rom", - - "g_p_ddrupctl", "g_clk_ddrupctl", - "g_p_ddrmon", "g_h_i2s0_8ch", - - "g_h_i2s1_8ch", "g_h_i2s2_2ch", - "g_h_spdif_8ch", "g_h_crypto_mst", - - "g_h_crypto_slv", "g_p_efuse_1024", - "g_p_efuse_256", "g_pclk_i2c0"; - - #clock-cells = <1>; - }; - - clk_gates9: gate-clk@00f4 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f4 0x4>; - clocks = - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&dummy>, - - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>, - - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>, - - <&pclk_bus>, <&pclk_bus>, - <&pclk_bus>, <&pclk_bus>; - - clock-output-names = - "g_pclk_i2c1", "g_pclk_i2c2", - "g_pclk_i2c3", "reserved", - - "g_pclk_timer0", "g_pclk_stimer", - "g_pclk_spi0", "g_pclk_rk_pwm", - - "g_pclk_gpio0", "g_pclk_gpio1", - "g_pclk_gpio2", "g_pclk_gpio3", - - "g_pclk_uart0", "g_pclk_uart1", - "g_pclk_uart2", "g_pclk_tsadc"; - - #clock-cells = <1>; - }; - - clk_gates10: gate-clk@00f8 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00f8 0x4>; - clocks = - <&pclk_bus>, <&aclk_bus>, - <&clk_gates6 13>, <&clk_gates6 4>, - - <&pclk_bus>, <&clk_gates6 4>, - <&pclk_bus>, <&clk_gates6 4>, - - <&clk_gates6 4>, <&clk_gates6 4>, - <&pclk_bus>, <&hclk_bus>, - - <&clkin_hsadc_tsp>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_pclk_grf", "g_aclk_bus", - "g_p_mschniu", "g_p_ddrphy", - - "g_pclk_cru", "g_p_acodecphy", - "g_pclk_sgrf", "g_p_hdmiphy", - - "g_p_vdacphy", "g_p_phy_noc", - "g_pclk_sim", "g_hclk_tsp", - - "clk_hsadc_tsp", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates11: gate-clk@00fc { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x00fc 0x4>; - clocks = - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&aclk_peri>, <&pclk_peri>, - <&hclk_peri>, <&hclk_peri>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&dummy>, - - <&hclk_peri>, <&hclk_peri>, - <&hclk_peri>, <&dummy>; - - clock-output-names = - "g_hclk_sdmmc", "g_hclk_sdio", - "g_clk_emmc", "g_clk_nandc", - - "g_aclk_gmac", "g_pclk_gmac", - "g_hclk_host0", "g_h_host0_arb", - - "g_hclk_host1", "g_h_host1_arb", - "g_hclk_host2", "reserved", - - "g_hclk_otg", "g_hclk_otg_pmu", - "g_h_host2_arb", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates12: gate-clk@0100 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0100 0x4>; - clocks = - <&aclk_peri>, <&hclk_peri>, - <&pclk_peri>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_a_peri_noc", "g_h_peri_noc", - "g_p_peri_noc", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates13: gate-clk@0104 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0104 0x4>; - clocks = - <&aclk_rga>, <&hclk_vio>, - <&aclk_iep>, <&hclk_vio>, - - <&dummy>, <&aclk_vop>, - <&hclk_vio>, <&hclk_vio>, - - <&hclk_vio>, <&aclk_iep>, - <&aclk_hdcp>, <&aclk_rga>, - - <&aclk_vop>, <&hclk_vio>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_aclk_rga", "g_hclk_rga", - "g_aclk_iep", "g_hclk_iep", - - "reserved", "g_aclk_vop", - "g_hclk_vop", "g_h_vio_ahbarbi", - - "g_h_vio_noc", "g_a_iep_noc", - "g_a_hdcp_noc", "g_a_rga_noc", - - "g_a_vop_noc", "g_h_vop_noc", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates14: gate-clk@0108 { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x0108 0x4>; - clocks = - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&hclk_vio>, <&hclk_vio>, - - <&dummy>, <&dummy>, - <&aclk_hdcp>, <&hclk_vio>, - - <&hclk_vio>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "g_p_hdmi_ctrl", "g_h_vio_h2p", - - "reserved", "reserved", - "g_aclk_hdcp", "g_pclk_hdcp", - - "g_h_hdcp_mmu", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - - clk_gates15: gate-clk@010c { - compatible = "rockchip,rk3188-gate-clk"; - reg = <0x010c 0x4>; - clocks = - <&aclk_vpu>, <&hclk_vpu>, - <&aclk_rkvdec>, <&hclk_rkvdec>, - - <&aclk_vpu>, <&hclk_vpu>, - <&aclk_rkvdec>, <&hclk_rkvdec>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "g_aclk_vpu", "g_hclk_vpu", - "g_a_rkvdec", "g_h_rkvdec", - - "g_a_vpu_noc", "g_h_vpu_noc", - "g_a_rkvdec_noc", "g_h_rkvdec_noc", - - "reserved", "reserved", - "reserved", "reserved", - - "reserved", "reserved", - "reserved", "reserved"; - - #clock-cells = <1>; - }; - }; - }; -}; -}; diff --git a/arch/arm/boot/dts/rk3228-fpga.dts b/arch/arm/boot/dts/rk3228-fpga.dts deleted file mode 100644 index 51eee57cb2ba..000000000000 --- a/arch/arm/boot/dts/rk3228-fpga.dts +++ /dev/null @@ -1,266 +0,0 @@ -/dts-v1/; - -#include -#include - -#include "skeleton.dtsi" -#include "rk3228-clocks.dtsi" - -/ { - compatible = "rockchip,rk3228"; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x10000000>; - }; - - chosen { - bootargs = "initrd=0x62000000,0x00180000 init=/init console=ttyFIQ0,115200 earlyprintk=uart8250-32bit,0x11030000"; - }; - - aliases { - serial2 = &uart_dbg; - }; - - uart_dbg: serial@11030000 { - compatible = "rockchip,serial"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&xin24m>, <&xin24m>; - clock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,signal-irq = <159>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ - rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ - //status = "disabled"; - }; - - ion { - compatible = "rockchip,ion"; - #address-cells = <1>; - #size-cells = <0>; - - /* - ion_carveout: rockchip,ion-heap@2 { - compatible = "rockchip,ion-heap"; - rockchip,ion_heap = <2>; - reg = <0x42000000 0xc00000>; - }; - */ - ion_cma: rockchip,ion-heap@4 { - compatible = "rockchip,ion-heap"; - rockchip,ion_heap = <4>; - reg = <0x00000000 0x4000000>; - }; - rockchip,ion-heap@0 { /* VMALLOC HEAP */ - compatible = "rockchip,ion-heap"; - rockchip,ion_heap = <0>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 - 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 - 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 - 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 - 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 - 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 - 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 - 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 - 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 - 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 - 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - 9 8 7 6 5 4 3 2 1 0>; - default-brightness-level = <200>; - }; - - vop: vop@20020000 { - compatible = "rockchip,rk3228-lcdc"; - backlight = <&backlight>; - - rockchip,cabc_mode = <0>; - rockchip,prop = <1>; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x20050000 0x300>; - interrupts = ; - clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - }; - - vop_mmu { - dbgname = "vop"; - compatible = "rockchip,vop_mmu"; - reg = <0x20053f00 0x100>; - interrupts = ; - interrupt-names = "vopb_mmu"; - }; - - fb: fb{ - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = <0>; - }; - - rk_screen: rk_screen{ - compatible = "rockchip,screen"; - disp_timings: display-timings { - native-mode = <&timing0>; - timing0: timing0 { - screen-type = ; - out-face = ; - clock-frequency = <27000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <206>; - hfront-porch = <40>; - vback-porch = <25>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - swap-rb = <0>; - swap-rg = <0>; - swap-gb = <0>; - }; - }; - }; - - rockchip_clocks_init: clocks-init{ - compatible = "rockchip,clocks-init"; - rockchip,clocks-init-parent = - <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>, - <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>, - <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>, - <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>, - <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>, - <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>, - <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>; - rockchip,clocks-init-rate = - <&clk_gpll 600000000>, <&clk_core 700000000>, - <&clk_cpll 500000000>, <&aclk_bus 250000000>, - <&hclk_bus 125000000>, <&pclk_bus 62500000>, - <&aclk_peri 250000000>, <&hclk_peri 125000000>, - <&pclk_peri 62500000>, <&clk_mac 125000000>, - <&aclk_iep 250000000>, <&hclk_vio 125000000>, - <&aclk_rga 250000000>, <&clk_gpu 250000000>, - <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>, - <&clk_vdec_cabac 250000000>; -/* - rockchip,clocks-uboot-has-init = - <&aclk_vio0>; -*/ - }; - - rockchip_clocks_enable: clocks-enable { - compatible = "rockchip,clocks-enable"; - clocks = - /*PLL*/ - <&clk_apll>, - <&clk_dpll>, - <&clk_gpll>, - <&clk_cpll>, - - /*PD_CORE*/ - <&clk_core>, - <&pclk_dbg>, - <&aclk_core>, - <&clk_gates4 2>, - - /*PD_BUS*/ - <&aclk_bus>, - <&hclk_bus>, - <&pclk_bus>, - <&clk_gates8 0>,/*aclk_intmem*/ - <&clk_gates8 1>,/*clk_intmem_mbist*/ - <&clk_gates8 2>,/*aclk_dmac_bus*/ - <&clk_gates10 1>,/*g_aclk_bus*/ - <&clk_gates13 9>,/*aclk_gic400*/ - <&clk_gates8 3>,/*hclk_rom*/ - <&clk_gates8 4>,/*pclk_ddrupctl*/ - <&clk_gates8 6>,/*pclk_ddrmon*/ - <&clk_gates9 4>,/*pclk_timer0*/ - <&clk_gates9 5>,/*pclk_stimer*/ - <&clk_gates10 0>,/*pclk_grf*/ - <&clk_gates10 4>,/*pclk_cru*/ - <&clk_gates10 6>,/*pclk_sgrf*/ - <&clk_gates10 3>,/*pclk_ddrphy*/ - <&clk_gates10 9>,/*pclk_phy_noc*/ - - /*PD_PERI*/ - <&aclk_peri>, - <&hclk_peri>, - <&pclk_peri>, - <&clk_gates12 0>,/*aclk_peri_noc*/ - <&clk_gates12 1>,/*hclk_peri_noc*/ - <&clk_gates12 2>,/*pclk_peri_noc*/ - - <&clk_gates6 5>, /* g_clk_timer0 */ - <&clk_gates6 6>, /* g_clk_timer1 */ - - <&clk_gates7 14>, /* g_aclk_gpu */ - <&clk_gates7 15>, /* g_aclk_gpu_noc */ - - <&clk_gates1 3>;/*clk_jtag*/ - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,amba-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - clocks = <&clk_gates8 2>; - clock-names = "apb_pclk"; - interrupts = , - ; - #dma-cells = <1>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3228-sdk.dts b/arch/arm/boot/dts/rk3228-sdk.dts deleted file mode 100755 index f4d7e682d1a4..000000000000 --- a/arch/arm/boot/dts/rk3228-sdk.dts +++ /dev/null @@ -1,295 +0,0 @@ -/dts-v1/; - -#include "rk3228.dtsi" -#include - -/ { - chosen { - bootargs = "vmalloc=496M psci=enable"; - }; - - fiq-debugger { - status = "disabled"; - }; - - wireless-wlan { - compatible = "wlan-platdata"; - /* wifi_chip_type - wifi chip define - * bcmwifi ==> like ap6xxx, rk90x; - * rtkwifi ==> like rtl8188xx, rtl8723xx,rtl8812auv; - * esp8089 ==> esp8089; - * other ==> for other wifi; - */ - wifi_chip_type = "bcmwifi"; - sdio_vref = <1800>; //1800mv or 3300mv - //keep_wifi_power_on; - //power_ctrl_by_pmu; - power_pmu_regulator = "act_ldo3"; - power_pmu_enable_level = <1>; //1->HIGH, 0->LOW - //vref_ctrl_enable; - //vref_ctrl_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_HIGH>; - vref_pmu_regulator = "act_ldo3"; - vref_pmu_enable_level = <1>; //1->HIGH, 0->LOW - WIFI,poweren_gpio = <&gpio2 GPIO_D2 GPIO_ACTIVE_HIGH>; - WIFI,host_wake_irq = <&gpio0 GPIO_D4 GPIO_ACTIVE_HIGH>; - //WIFI,reset_gpio = <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - - wireless-bluetooth { - compatible = "bluetooth-platdata"; - //wifi-bt-power-toggle; - //uart_rts_gpios = <&gpio2 GPIO_D5 GPIO_ACTIVE_LOW>; - //pinctrl-names = "default","rts_gpio"; - //pinctrl-0 = <&uart1_rts>; - //pinctrl-1 = <&uart1_rts_gpio>; - //BT,power_gpio = <&gpio4 GPIO_D3 GPIO_ACTIVE_HIGH>; - BT,reset_gpio = <&gpio2 GPIO_D5 GPIO_ACTIVE_HIGH>; - BT,wake_gpio = <&gpio3 GPIO_D3 GPIO_ACTIVE_HIGH>; - BT,wake_host_irq = <&gpio3 GPIO_D2 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - pwm-regulator1 { - compatible = "rockchip_pwm_regulator"; - pwms = <&pwm1 0 2000>; - rockchip,pwm_id= <1>; - rockchip,pwm_voltage_map= <950000 975000 1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000 1325000 1350000 1375000 1400000>; - rockchip,pwm_voltage= <1100000>; - rockchip,pwm_min_voltage= <950000>; - rockchip,pwm_max_voltage= <1450000>; - rockchip,pwm_suspend_voltage= <950000>; - rockchip,pwm_coefficient= <475>; - status = "okay"; - regulators { - #address-cells = <1>; - #size-cells = <0>; - pwm_reg0: regulator@0 { - regulator-compatible = "pwm_dcdc1"; - regulator-name= "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1450000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - - pwm-regulator2 { - compatible = "rockchip_pwm_regulator"; - pwms = <&pwm2 0 25000>; - rockchip,pwm_id= <2>; - rockchip,pwm_voltage_map= <1000000 1025000 1050000 1075000 1100000 1125000 1150000 1175000 1200000 1225000 1250000 1275000 1300000>; - rockchip,pwm_voltage= <1200000>; - rockchip,pwm_min_voltage= <1000000>; - rockchip,pwm_max_voltage= <1300000>; - rockchip,pwm_suspend_voltage= <1250000>; - rockchip,pwm_coefficient= <475>; - status = "okay"; - regulators { - #address-cells = <1>; - #size-cells = <0>; - pwm_reg1: regulator@1 { - regulator-compatible = "pwm_dcdc2"; - regulator-name= "vdd_logic"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; -}; - -&nandc { - status = "okay"; //used nand set "okay" ,used emmc set "disabled" -}; - -&emmc { - clock-frequency = <50000000>; - clock-freq-min-max = <400000 50000000>; - supports-highspeed; - supports-emmc; - bootpart-no-access; - supports-DDR_MODE; - ignore-pm-notify; - keep-power-in-suspend; - status = "okay"; -}; - -&sdmmc { - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - supports-highspeed; - supports-sd; - broken-cd; - card-detect-delay = <200>; - ignore-pm-notify; - keep-power-in-suspend; - status = "okay"; -}; - -&sdio { - clock-frequency = <37500000>; - clock-freq-min-max = <200000 37500000>; - supports-highspeed; - supports-sdio; - ignore-pm-notify; - keep-power-in-suspend; - cap-sdio-irq; - status = "okay"; -}; - -&uart1{ - status = "okay"; - dma-names = "!tx", "!rx"; - //pinctrl-0 = <&uart1_xfer &uart1_cts>; -}; - -&i2c0 { - status = "okay"; - rtc@51 { - compatible = "rtc,hym8563"; - reg = <0x51>; - irq_gpio = <&gpio0 GPIO_A4 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -/* - * Due to not have the software of PWM for remotectrl. - * We can _*HACK*_ do that as the following. - */ -&pwm3 { - compatible = "rockchip,remotectl-pwm"; - remote_pwm_id = <3>; - handle_cpu_id = <1>; - status = "okay"; - - ir_key1{ - rockchip,usercode = <0x4040>; - rockchip,key_table = - <0xf2 KEY_REPLY>, - <0xba KEY_BACK>, - <0xf4 KEY_UP>, - <0xf1 KEY_DOWN>, - <0xef KEY_LEFT>, - <0xee KEY_RIGHT>, - <0xbd KEY_HOME>, - <0xea KEY_VOLUMEUP>, - <0xe3 KEY_VOLUMEDOWN>, - <0xe2 KEY_SEARCH>, - <0xb2 KEY_POWER>, - <0xbc KEY_MUTE>, - <0xec KEY_MENU>, - <0xbf 0x190>, - <0xe0 0x191>, - <0xe1 0x192>, - <0xe9 183>, - <0xe6 248>, - <0xe8 185>, - <0xe7 186>, - <0xf0 388>, - <0xbe 0x175>; - }; - ir_key2{ - rockchip,usercode = <0xff00>; - rockchip,key_table = - <0xf9 KEY_HOME>, - <0xbf KEY_BACK>, - <0xfb KEY_MENU>, - <0xaa KEY_REPLY>, - <0xb9 KEY_UP>, - <0xe9 KEY_DOWN>, - <0xb8 KEY_LEFT>, - <0xea KEY_RIGHT>, - <0xeb KEY_VOLUMEDOWN>, - <0xef KEY_VOLUMEUP>, - <0xf7 KEY_MUTE>, - <0xe7 KEY_POWER>, - <0xfc KEY_POWER>, - <0xa9 KEY_VOLUMEDOWN>, - <0xa8 KEY_VOLUMEDOWN>, - <0xe0 KEY_VOLUMEDOWN>, - <0xa5 KEY_VOLUMEDOWN>, - <0xab 183>, - <0xb7 388>, - <0xf8 184>, - <0xaf 185>, - <0xed KEY_VOLUMEDOWN>, - <0xee 186>, - <0xb3 KEY_VOLUMEDOWN>, - <0xf1 KEY_VOLUMEDOWN>, - <0xf2 KEY_VOLUMEDOWN>, - <0xf3 KEY_SEARCH>, - <0xb4 KEY_VOLUMEDOWN>, - <0xbe KEY_SEARCH>; - }; - ir_key3{ - rockchip,usercode = <0x1dcc>; - rockchip,key_table = - <0xee KEY_REPLY>, - <0xf0 KEY_BACK>, - <0xf8 KEY_UP>, - <0xbb KEY_DOWN>, - <0xef KEY_LEFT>, - <0xed KEY_RIGHT>, - <0xfc KEY_HOME>, - <0xf1 KEY_VOLUMEUP>, - <0xfd KEY_VOLUMEDOWN>, - <0xb7 KEY_SEARCH>, - <0xff KEY_POWER>, - <0xf3 KEY_MUTE>, - <0xbf KEY_MENU>, - <0xf9 0x191>, - <0xf5 0x192>, - <0xb3 388>, - <0xbe KEY_1>, - <0xba KEY_2>, - <0xb2 KEY_3>, - <0xbd KEY_4>, - <0xf9 KEY_5>, - <0xb1 KEY_6>, - <0xfc KEY_7>, - <0xf8 KEY_8>, - <0xb0 KEY_9>, - <0xb6 KEY_0>, - <0xb5 KEY_BACKSPACE>; - }; -}; - -&gmac_clkin { - clock-frequency = <125000000>; -}; - -&gmac { - /* pmu_regulator = "act_ldo5"; */ - /* power-gpio = <&gpio0 GPIO_A6 GPIO_ACTIVE_HIGH>; */ - /* reset-gpio = <&gpio3 GPIO_B4 GPIO_ACTIVE_LOW>; */ - /* phyirq-gpio = <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>; */ - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins>; - clock_in_out = "input"; - tx_delay = <0x30>; - rx_delay = <0x10>; -}; diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi deleted file mode 100755 index ea548866c031..000000000000 --- a/arch/arm/boot/dts/rk3228.dtsi +++ /dev/null @@ -1,1355 +0,0 @@ -#include -#include - -#include "skeleton.dtsi" -#include "rk3228-clocks.dtsi" - -#include -#include -#include - -/ { - compatible = "rockchip,rk3228"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - }; - }; - - psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>; - }; - - sgrf: syscon@10140000 { - compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon"; - reg = <0x10140000 0x1000>; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon"; - reg = <0x11000000 0x1000>; - }; - - cru: syscon@110e0000 { - compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon"; - reg = <0x110e0000 0x1000>; - }; - - ddrpctl: syscon@11200000 { - compatible = "rockchip,rk3228-ddrpctl", "syscon"; - reg = <0x11200000 0x400>; - }; - - msch: syscon@31020000 { - compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon"; - reg = <0x31020000 0x3000>; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - }; - - reset: reset@110e0110{ - compatible = "rockchip,reset"; - reg = <0x110e0110 0x20>; - rockchip,reset-flag = ; - #reset-cells = <1>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - fiq-debugger { - compatible = "rockchip,fiq-debugger"; - rockchip,serial-id = <2>; - rockchip,signal-irq = <159>; - rockchip,wake-irq = <0>; - rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ - rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ - status = "disabled"; - }; - - rockchip_ion: rockchip-ion { - compatible = "rockchip,ion"; - #address-cells = <1>; - #size-cells = <0>; - - ion_cma: cma-heap { - compatible = "rockchip,ion-heap"; - status = "disabled"; - rockchip,ion_heap = <4>; - reg = <0x10000000 0x08000000>; /* 128 MB */ - }; - system_heap: system-heap { - compatible = "rockchip,ion-heap"; - rockchip,ion_heap = <0>; - }; - }; - - dram: dram { - compatible = "rockchip,rk3228-dram"; - status = "okay"; - dram_freq = <600000000>; - rockchip,dram_timing = <&dram_timing>; - }; - - rockchip_clocks_init: clocks-init{ - compatible = "rockchip,clocks-init"; - rockchip,clocks-init-parent = - <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>, - <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>, - <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>, - <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>, - <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>, - <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>, - <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>; - rockchip,clocks-init-rate = - <&clk_gpll 600000000>, <&clk_core 700000000>, - <&clk_cpll 500000000>, <&aclk_bus 250000000>, - <&hclk_bus 125000000>, <&pclk_bus 62500000>, - <&aclk_peri 250000000>, <&hclk_peri 125000000>, - <&pclk_peri 62500000>, <&clk_mac 125000000>, - <&aclk_iep 250000000>, <&hclk_vio 125000000>, - <&aclk_rga 250000000>, <&clk_gpu 250000000>, - <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>, - <&clk_vdec_cabac 250000000>; -/* - rockchip,clocks-uboot-has-init = - <&aclk_vio0>; -*/ - }; - - rockchip_clocks_enable: clocks-enable { - compatible = "rockchip,clocks-enable"; - clocks = - /*PLL*/ - <&clk_apll>, - <&clk_dpll>, - <&clk_gpll>, - <&clk_cpll>, - - /*PD_CORE*/ - <&clk_core>, - <&pclk_dbg>, - <&aclk_core>, - <&clk_gates4 2>, - - /*PD_BUS*/ - <&aclk_bus>, - <&hclk_bus>, - <&pclk_bus>, - <&clk_gates8 0>,/*aclk_intmem*/ - <&clk_gates8 1>,/*clk_intmem_mbist*/ - <&clk_gates8 2>,/*aclk_dmac_bus*/ - <&clk_gates10 1>,/*g_aclk_bus*/ - <&clk_gates13 9>,/*aclk_gic400*/ - <&clk_gates8 3>,/*hclk_rom*/ - <&clk_gates8 4>,/*pclk_ddrupctl*/ - <&clk_gates8 6>,/*pclk_ddrmon*/ - <&clk_gates9 4>,/*pclk_timer0*/ - <&clk_gates9 5>,/*pclk_stimer*/ - <&clk_gates10 0>,/*pclk_grf*/ - <&clk_gates10 4>,/*pclk_cru*/ - <&clk_gates10 6>,/*pclk_sgrf*/ - <&clk_gates10 3>,/*pclk_ddrphy*/ - <&clk_gates10 9>,/*pclk_phy_noc*/ - - /*PD_PERI*/ - <&aclk_peri>, - <&hclk_peri>, - <&pclk_peri>, - <&clk_gates12 0>,/*aclk_peri_noc*/ - <&clk_gates12 1>,/*hclk_peri_noc*/ - <&clk_gates12 2>,/*pclk_peri_noc*/ - - <&clk_gates6 5>, /* g_clk_timer0 */ - <&clk_gates6 6>, /* g_clk_timer1 */ - - <&clk_gates7 14>, /* g_aclk_gpu */ - <&clk_gates7 15>, /* g_aclk_gpu_noc */ - - <&clk_gates1 3>;/*clk_jtag*/ - }; - - uart0: serial@11010000 { - compatible = "rockchip,serial"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&clk_uart0>, <&clk_gates9 12>; - clock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&pdma 2>, <&pdma 3>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "rockchip,serial"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&clk_uart1>, <&clk_gates9 13>; - clock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&pdma 4>, <&pdma 5>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "rockchip,serial"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&clk_uart2>, <&clk_gates9 14>; - lock-names = "sclk_uart", "pclk_uart"; - reg-shift = <2>; - reg-io-width = <4>; - dmas = <&pdma 6>, <&pdma 7>; - #dma-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - status = "disabled"; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk30-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c0_xfer>; - pinctrl-1 = <&i2c0_gpio>; - pinctrl-2 = <&i2c0_sleep>; - gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, - <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>; - clocks = <&clk_gates8 15>; - rockchip,check-idle = <1>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk30-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c1_xfer>; - pinctrl-1 = <&i2c1_gpio>; - pinctrl-2 = <&i2c1_sleep>; - gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, - <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>; - clocks = <&clk_gates9 0>; - rockchip,check-idle = <1>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk30-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c2_xfer>; - pinctrl-1 = <&i2c2_gpio>; - pinctrl-2 = <&i2c2_sleep>; - gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, - <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>; - clocks = <&clk_gates9 1>; - rockchip,check-idle = <1>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk30-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "gpio", "sleep"; - pinctrl-0 = <&i2c3_xfer>; - pinctrl-1 = <&i2c3_gpio>; - pinctrl-2 = <&i2c3_sleep>; - gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, - <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>; - clocks = <&clk_gates9 2>; - rockchip,check-idle = <1>; - status = "disabled"; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "arm,amba-bus"; - interrupt-parent = <&gic>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - clocks = <&clk_gates8 2>; - clock-names = "apb_pclk"; - interrupts = , - ; - #dma-cells = <1>; - }; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip-i2s"; - reg = <0x100c0000 0x1000>; - i2s-id = <0>; - clocks = <&clk_i2s0>, <&clk_gates8 7>; - clock-names = "i2s_clk", "i2s_hclk"; - interrupts = ; - dmas = <&pdma 11>, <&pdma 12>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip-i2s"; - reg = <0x100b0000 0x1000>; - i2s-id = <1>; - clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>; - clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk"; - interrupts = ; - dmas = <&pdma 14>, <&pdma 15>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip-i2s"; - reg = <0x100e0000 0x1000>; - i2s-id = <2>; - clocks = <&clk_i2s2>, <&clk_gates8 9>; - clock-names = "i2s_clk", "i2s_hclk"; - interrupts = ; - dmas = <&pdma 0>, <&pdma 1>; - #dma-cells = <2>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip-spdif"; - reg = <0x100d0000 0x1000>; - clocks = <&clk_spdif>, <&clk_gates8 10>; - clock-names = "spdif_mclk", "spdif_hclk"; - interrupts = ; - dmas = <&pdma 10>; - #dma-cells = <1>; - dma-names = "tx"; - status = "disabled"; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clock-frequency = <32768>; - clocks = <&clk_tsadc>, <&clk_gates9 15>; - resets = <&reset RK3228_RST_TSADC>; - reset-names = "tsadc-apb"; - #thermal-sensor-cells = <1>; - hw-shut-temp = <120000>; - pinctrl-names = "default"; - pinctrl-0 = <&tsadc_gpio>; - tsadc-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - tsadc-tshut-polarity = <0>;/* tshut polarity 0:LOW 1:HIGH */ - status = "okay"; - }; - - gpu { - compatible = "arm,mali400"; - reg = <0x20001000 0x200>, - <0x20000000 0x100>, - <0x20003000 0x100>, - <0x20008000 0x1100>, - <0x20004000 0x100>, - <0x2000A000 0x1100>, - <0x20005000 0x100>; - - reg-names = "Mali_L2", - "Mali_GP", - "Mali_GP_MMU", - "Mali_PP0", - "Mali_PP0_MMU", - "Mali_PP1", - "Mali_PP1_MMU"; - - interrupts = , - , - , - , - , - ; - - interrupt-names = "Mali_GP_IRQ", - "Mali_GP_MMU_IRQ", - "Mali_PP0_IRQ", - "Mali_PP0_MMU_IRQ", - "Mali_PP1_IRQ", - "Mali_PP1_MMU_IRQ"; - }; - - fb: fb { - compatible = "rockchip,rk-fb"; - rockchip,disp-mode = ; - }; - - rk_screen: rk_screen { - compatible = "rockchip,screen"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk-pwm"; - reg = <0x110b0000 0x10>; - /* used by driver on remotectl'pwm */ - interrupts = ; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&clk_gates9 7>; - clock-names = "pclk_pwm"; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk-pwm"; - reg = <0x110b0010 0x10>; - /* used by driver on remotectl'pwm */ - interrupts = ; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&clk_gates9 7>; - clock-names = "pclk_pwm"; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk-pwm"; - reg = <0x110b0020 0x10>; - /* used by driver on remotectl'pwm */ - interrupts = ; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&clk_gates9 7>; - clock-names = "pclk_pwm"; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk-pwm"; - reg = <0x110b0030 0x10>; - /* used by driver on remotectl'pwm */ - interrupts = ; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwmir_pin>; - clocks = <&clk_gates9 7>; - clock-names = "pclk_pwm"; - status = "disabled"; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-lcdc"; - - rockchip,cabc_mode = <0>; - rockchip,pwr18 = <0>; - rockchip,iommu-enabled = <1>; - reg = <0x20050000 0x300>; - interrupts = ; - clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>; - clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; - }; - - vop_mmu { - dbgname = "vop"; - compatible = "rockchip,vop_mmu"; - reg = <0x20053f00 0x100>; - interrupts = ; - interrupt-names = "vop_mmu"; - }; - - hevc_mmu { - dbgname = "hevc"; - compatible = "rockchip,hevc_mmu"; - reg = <0x20034440 0x40>, - <0x20034480 0x40>; - interrupts = ; - interrupt-names = "hevc_mmu"; - }; - - vpu_mmu { - dbgname = "vpu"; - compatible = "rockchip,vpu_mmu"; - reg = <0x20026800 0x100>; - interrupts = ; - interrupt-names = "vpu_mmu"; - }; - - iep_mmu { - dbgname = "iep"; - compatible = "rockchip,iep_mmu"; - reg = <0x20078800 0x100>; - interrupts = ; - interrupt-names = "iep_mmu"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-hdmi"; - reg = <0x200a0000 0x20000>, - <0x12030000 0x10000>; - interrupts = , - ; - clocks = <&clk_gates3 7>, - <&clk_gates14 6>, - <&clk_gates10 7>, - <&clk_hdmi_cec>; - clock-names = "hdcp_clk_hdmi", - "pclk_hdmi", - "pclk_hdmi_phy", - "cec_clk_hdmi"; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&hdmi_cec &hdmii2c_xfer>; - pinctrl-1 = <&i2c3_gpio>; - rockchip,hotplug = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>; - rockchip,hdmi_audio_source = <0>; - rockchip,hdcp_enable = <0>; - rockchip,cec_enable = <0>; - status = "disabled"; - }; - - hdmi_hdcp2: hdmi_hdcp2@20090000 { - compatible = "rockchip,rk3228-hdmi-hdcp2"; - reg = <0x20090000 0x10000>; - interrupts = ; - clocks = <&aclk_hdcp>, - <&clk_gates14 12>, - <&clk_gates14 11>, - <&clk_hdcp>; - clock-names = "aclk_hdcp2", - "hclk_hdcp2_mmu", - "pclk_hdcp2", - "hdcp2_clk_hdmi"; - status = "disabled"; - }; - - tve: tve { - compatible = "rockchip,rk3228-tve"; - reg = <0x20053e00 0x100>, - <0x12020000 0x10000>; - clocks = <&clk_gates10 8>; - clock-names = "pclk_vdac"; - status = "disabled"; - }; - - emmc: rksdmmc@30020000 { - compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc"; - reg = <0x30020000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk_emmc>, <&clk_gates11 2>; - clock-names = "clk_mmc", "hclk_mmc"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <8>; - cru_regsbase = <0x124>; - cru_reset_offset = <3>; - }; - - sdmmc: rksdmmc@30000000 { - compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc"; - reg = <0x30000000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>; - pinctrl-1 = <&sdmmc_gpio>; - cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>; /* CD GPIO */ - clocks = <&clk_sdmmc0>, <&clk_gates11 0>; - clock-names = "clk_mmc", "hclk_mmc"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <4>; - cru_regsbase = <0x124>; - cru_reset_offset = <1>; - }; - - sdio: rksdmmc@30010000 { - compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc"; - reg = <0x30010000 0x10000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default", "idle"; - pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>; - pinctrl-1 = <&sdio0_gpio>; - clocks = <&clk_sdio>, <&clk_gates11 1>; - clock-names = "clk_mmc", "hclk_mmc"; - num-slots = <1>; - fifo-depth = <0x100>; - bus-width = <4>; - cru_regsbase = <0x124>; - cru_reset_offset = <2>; - }; - - nandc: nandc@30030000 { - compatible = "rockchip,rk-nandc"; - reg = <0x30030000 0x4000>; - interrupts = ; - nandc_id = <0>; - clocks = <&clk_nandc>, <&clk_gates1 0>, <&clk_gates11 3>; - clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc"; - }; - - otg: usb@30040000 { - compatible = "rockchip,rk3228_usb20_otg"; - reg = <0x30040000 0x40000>; - interrupts = ; - clocks = <&clk_gates1 5>, <&clk_gates11 12>; - clock-names = "clk_usbphy0", "hclk_usb0"; - resets = <&reset RK3228_RST_USBOTG0>, <&reset RK3228_RST_UTMI0>, - <&reset RK3228_RST_OTGC0>; - reset-names = "otg_ahb", "otg_phy", "otg_controller"; - /*0 - Normal, 1 - Force Host, 2 - Force Device*/ - rockchip,usb-mode = <0>; - }; - - ehci0: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = ; - clocks = <&clk_gates1 6>, <&clk_gates11 6>; - clock-names = "clk_usbphy1", "hclk_host0"; - resets = <&reset RK3228_RST_USBHOST0>, <&reset RK3228_RST_UTMI1>, - <&reset RK3228_RST_HOST_CTRL0>; - reset-names = "host_ahb", "host_phy", "host_controller"; - }; - - ohci0: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = ; - }; - - ehci1: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = ; - clocks = <&clk_gates1 6>, <&clk_gates11 8>; - clock-names = "clk_usbphy1", "hclk_host0"; - resets = <&reset RK3228_RST_USBHOST1>, <&reset RK3228_RST_UTMI2>, - <&reset RK3228_RST_HOST_CTRL1>; - reset-names = "host_ahb", "host_phy", "host_controller"; - }; - - ohci1: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = ; - }; - - ehci2: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = ; - clocks = <&clk_gates1 6>, <&clk_gates11 10>; - clock-names = "clk_usbphy1", "hclk_host0"; - resets = <&reset RK3228_RST_USBHOST2>, <&reset RK3228_RST_UTMI3>, - <&reset RK3228_RST_HOST_CTRL2>; - reset-names = "host_ahb", "host_phy", "host_controller"; - }; - - ohci2: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = ; - }; - - gmac: eth@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - rockchip,grf = <&grf>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&clk_mac>, <&clk_gates5 5>, - <&clk_gates5 6>, <&clk_gates5 3>, - <&clk_gates5 4>, <&clk_gates11 4>, - <&clk_gates11 5>; - clock-names = "clk_mac", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&clk_gates9 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&clk_gates9 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&clk_gates9 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&clk_gates9 11>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_down_drv_12ma: pcfg-pull-down-drv-12ma { - bias-pull-down; - drive-strength = <12>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>, - <0 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>; - }; - i2c0_gpio: i2c0-gpio { - rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - i2c0_sleep: i2c0-sleep { - rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_input_high>, - <0 GPIO_A1 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>, - <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>; - }; - i2c1_gpio: i2c1-gpio { - rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - i2c1_sleep: i2c1-sleep { - rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_input_high>, - <0 GPIO_A3 RK_FUNC_GPIO &pcfg_input_high>; - - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>; - }; - i2c2_gpio: i2c2-gpio { - rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>, - <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - i2c2_sleep: i2c2-sleep { - rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>, - <2 GPIO_C4 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>, - <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>; - }; - i2c3_gpio: i2c3-gpio { - rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - i2c3_sleep: i2c3-sleep { - rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>, - <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_up>, - <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_up>, - <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart11 { - uart11_xfer: uart11-xfer { - rockchip,pins = <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_up>, - <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart11_cts: uart11-cts { - rockchip,pins = <3 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart11_rts: uart11-rts { - rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up>, - <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart21 { - uart21_xfer: uart21-xfer { - rockchip,pins = <1 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>, - <1 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 GPIO_C7 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 GPIO_A2 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 GPIO_A0 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 GPIO_A1 RK_FUNC_2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_up>; - }; - }; - - i2s { - i2s_mclk: i2s-mclk { - rockchip,pins = <0 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_sclk:i2s-sclk { - rockchip,pins = <0 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_lrckrx:i2s-lrckrx { - rockchip,pins = <0 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_lrcktx:i2s-lrcktx { - rockchip,pins = <0 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_sdi:i2s-sdi { - rockchip,pins = <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_sdo0:i2s-sdo0 { - rockchip,pins = <0 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>; - }; - - i2s_sdo1:i2s-sdo1 { - rockchip,pins = <1 GPIO_A2 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2s_sdo2:i2s-sdo2 { - rockchip,pins = <1 GPIO_A4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2s_sdo3:i2s-sdo3 { - rockchip,pins = <1 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2s_gpio: i2s-gpio { - rockchip,pins = <0 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>, - <0 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>, - <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_none>, - <1 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - spdif0 { - spdif0_tx: spdif0-tx { - rockchip,pins = <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - spdif1 { - spdif1_tx: spdif1-tx { - rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_dectn: sdmmc-dectn { - rockchip,pins = <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_wrprt: sdmmc-wrprt { - rockchip,pins = <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_pwren: sdmmc-pwren { - rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_gpio: sdmmc-gpio { - rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>; - }; - }; - - sdio0 { - sdio0_bus1: sdio0-bus1 { - rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdio0_bus4: sdio0-bus4 { - rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdio0_cmd: sdio0-cmd { - rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>; - }; - - sdio0_clk: sdio0-clk { - rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdio0_pwren: sdio0-pwren { - rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio0_gpio: sdio0-gpio { - rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>; - }; - }; - - - sdio1 { - sdio1_bus1: sdio1-bus1 { - rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdio1_bus4: sdio1-bus4 { - rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdio1_cmd: sdio1-cmd { - rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>; - }; - - sdio1_clk: sdio1-clk { - rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdio1_pwren: sdio1-pwren { - rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>; - }; - - sdio1_gpio: sdio1-gpio { - rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>, - <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 GPIO_C6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>; - }; - - emmc_pwren: emmc-pwren { - rockchip,pins = <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_rstnout: emmc_rstnout { - rockchip,pins = <1 GPIO_C7 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, - <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwmir { - pwmir_pin: pwmir-pin { - rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm10 { - pwm10_pin: pwm10-pin { - rockchip,pins = <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm11 { - pwm11_pin: pwm11-pin { - rockchip,pins = <0 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm12 { - pwm12_pin: pwm12-pin { - rockchip,pins = <1 GPIO_B4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm1ir { - pwm1ir_pin: pwm1ir-pin { - rockchip,pins = <1 GPIO_B3 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, - <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>, - <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - tsadc_pin { - tsadc_int: tsadc-int { - rockchip,pins = <0 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>; - }; - tsadc_gpio: tsadc-gpio { - rockchip,pins = <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hdmi_pin { - hdmi_cec: hdmi-cec { - rockchip,pins = <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>; - }; - - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - hdmi_i2c { - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 GPIO_A6 RK_FUNC_2 &pcfg_pull_none>, - <0 GPIO_A7 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3228_dram_default_timing.dtsi b/arch/arm/boot/dts/rk3228_dram_default_timing.dtsi deleted file mode 100755 index 129a85d758ee..000000000000 --- a/arch/arm/boot/dts/rk3228_dram_default_timing.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2014-2015 ROCKCHIP, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include - -/ { - dram_timing: dram_timing { - compatible = "rockchip,dram-timing"; - dram_spd_bin = ; - sr_idle = <1>; - pd_idle = <0x20>; - dram_dll_disb_freq = <300>; - phy_dll_disb_freq = <400>; - dram_odt_disb_freq = <333>; - phy_odt_disb_freq = <333>; - ddr3_drv = ; - ddr3_odt = ; - lpddr3_drv = ; - lpddr3_odt = ; - lpddr2_drv = ; - /* lpddr2 not supported odt */ - phy_clk_drv = ; - phy_cmd_drv = ; - phy_dqs_drv = ; - phy_odt = ; - }; -};