From: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Date: Thu, 27 Jun 2013 09:42:10 +0000 (+0000)
Subject: [SystemZ] Allow LA and LARL to be rematerialized
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7d884e4636fcd9572c5a00aec9bfcb97a0244172;p=oota-llvm.git

[SystemZ] Allow LA and LARL to be rematerialized


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185069 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 7debcdd506a..ff0d5665dfa 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -417,7 +417,8 @@ def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, GR64>;
 //===----------------------------------------------------------------------===//
 
 // Load BDX-style addresses.
-let neverHasSideEffects = 1, Function = "la" in {
+let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
+    Function = "la" in {
   let PairType = "12" in
     def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
                     "la\t$R1, $XBD2",
@@ -430,7 +431,8 @@ let neverHasSideEffects = 1, Function = "la" in {
 
 // Load a PC-relative address.  There's no version of this instruction
 // with a 16-bit offset, so there's no relaxation.
-let neverHasSideEffects = 1 in {
+let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
+    isReMaterializable = 1 in {
   def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
                      "larl\t$R1, $I2",
                      [(set GR64:$R1, pcrel32:$I2)]>;
diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll
index 0d343128c4c..6c60a2e96fc 100644
--- a/test/CodeGen/SystemZ/frame-01.ll
+++ b/test/CodeGen/SystemZ/frame-01.ll
@@ -3,6 +3,8 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare void @foo(i32 *)
+
 ; The CFA offset is 160 (the caller-allocated part of the frame) + 168.
 define void @f1(i64 %x) {
 ; CHECK: f1:
@@ -108,3 +110,17 @@ define void @f7(i64 %x) {
   store volatile i64 %x, i64* %ptr
   ret void
 }
+
+; Make sure that LA can be rematerialized.
+define void @f8() {
+; CHECK: f8:
+; CHECK: la %r2, 164(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: la %r2, 164(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i32
+  call void @foo(i32 *%ptr)
+  call void @foo(i32 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/la-01.ll b/test/CodeGen/SystemZ/la-01.ll
index b43e3f8662d..1ebe109ee00 100644
--- a/test/CodeGen/SystemZ/la-01.ll
+++ b/test/CodeGen/SystemZ/la-01.ll
@@ -15,6 +15,8 @@ define void @df() {
   ret void
 }
 
+declare void @foo(i32 *)
+
 ; Test a load of a fully-aligned external variable.
 define i32 *@f1() {
 ; CHECK: f1:
@@ -78,3 +80,16 @@ define void() *@f8() {
 ; CHECK-NEXT: br %r14
   ret void() *@df
 }
+
+; Test that LARL can be rematerialized.
+define i32 @f9() {
+; CHECK: f9:
+; CHECK: larl %r2, d2
+; CHECK: brasl %r14, foo@PLT
+; CHECK: larl %r2, d2
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  call void @foo(i32 *@d2)
+  call void @foo(i32 *@d2)
+  ret i32 0
+}
diff --git a/test/DebugInfo/SystemZ/variable-loc.ll b/test/DebugInfo/SystemZ/variable-loc.ll
index e6f4ff99dd4..a5ecdb9e7d1 100644
--- a/test/DebugInfo/SystemZ/variable-loc.ll
+++ b/test/DebugInfo/SystemZ/variable-loc.ll
@@ -8,8 +8,7 @@
 ;
 ; CHECK: main:
 ; CHECK: aghi    %r15, -568
-; CHECK: la      [[MAIN_ARR:%r[0-9]+]], 164(%r11)
-; CHECK: lgr     %r2, [[MAIN_ARR]]
+; CHECK: la      %r2, 164(%r11)
 ; CHECK: brasl   %r14, populate_array@PLT
 ;
 ; Now check that the debugging information reflects this: