From: Evan Cheng Date: Fri, 18 Apr 2008 20:55:36 +0000 (+0000) Subject: - Fix atomic operation JIT encoding. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7e03280b535242c1f394348702a1d1840b75774c;p=oota-llvm.git - Fix atomic operation JIT encoding. - Remove unused instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49921 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 5a788c057de..70dc926c798 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -471,7 +471,10 @@ void Emitter::emitInstruction(const MachineInstr &MI, unsigned NumOps = Desc->getNumOperands(); unsigned CurOp = 0; if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) - CurOp++; + ++CurOp; + else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) + // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 + --NumOps; unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc); switch (Desc->TSFlags & X86II::FormMask) { diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index effb305e3c8..a181e06d6d7 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1107,29 +1107,20 @@ def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), // Atomic Instructions //===----------------------------------------------------------------------===// -//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and -// prefixes should be correct - let Defs = [RAX, EFLAGS], Uses = [RAX] in { -def CMPXCHG64 : RI<0xB1, Pseudo, (outs), (ins i64mem:$ptr, GR64:$swap), - "cmpxchgq $swap,$ptr", []>, TB; -def LCMPXCHG64 : RI<0xB1, Pseudo, (outs), (ins i64mem:$ptr, GR64:$swap), +def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), "lock cmpxchgq $swap,$ptr", [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK; } let Constraints = "$val = $dst", Defs = [EFLAGS] in { -def LXADD64 : RI<0xC1, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), +def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val), "lock xadd $val, $ptr", [(set GR64:$dst, (atomic_las_64 addr:$ptr, GR64:$val))]>, TB, LOCK; -def XADD64 : RI<0xC1, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), - "xadd $val, $ptr", []>, TB; -def LXCHG64 : RI<0x87, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), +def LXCHG64 : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val), "lock xchg $val, $ptr", [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>, LOCK; -def XCHG64 : RI<0x87, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val), - "xchg $val, $ptr", []>; } diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 3ba6af4f090..b57fdb31157 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2543,75 +2543,57 @@ def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr), // Atomic support // -//FIXME: Please check the format Pseudo is certainly wrong, but the opcode and -// prefixes should be correct - +// Atomic compare and swap. let Defs = [EAX, EFLAGS], Uses = [EAX] in { -def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap), - "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", []>, TB; -def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap), +def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap), "lock cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}", [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK; } let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in { -def CMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr), - "cmpxchg8b\t$ptr", []>, TB; -def LCMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr), +def LCMPXCHG8B : I<0xC7, MRMDestMem, (outs), (ins i32mem:$ptr), "lock cmpxchg8b\t$ptr", [(X86cas8 addr:$ptr)]>, TB, LOCK; } let Defs = [AX, EFLAGS], Uses = [AX] in { -def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap), - "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", []>, TB, OpSize; -def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap), +def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap), "lock cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}", [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK; } let Defs = [AL, EFLAGS], Uses = [AL] in { -def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), - "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", []>, TB; -def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap), +def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap), "lock cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}", [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK; } +// Atomic swap +let Constraints = "$val = $dst", Defs = [EFLAGS] in { +def LXCHG32 : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), + "lock xchg{l}\t{$val, $ptr|$ptr, $val}", + [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK; +def LXCHG16 : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), + "lock xchg{w}\t{$val, $ptr|$ptr, $val}", + [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, + OpSize, LOCK; +def LXCHG8 : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), + "lock xchg{b}\t{$val, $ptr|$ptr, $val}", + [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK; +} + +// Atomic exchange and add let Constraints = "$val = $dst", Defs = [EFLAGS] in { -def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), +def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), "lock xadd{l}\t{$val, $ptr|$ptr, $val}", [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>, TB, LOCK; -def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), +def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), "lock xadd{w}\t{$val, $ptr|$ptr, $val}", [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>, TB, OpSize, LOCK; -def LXADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), +def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), "lock xadd{b}\t{$val, $ptr|$ptr, $val}", [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>, TB, LOCK; -def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), - "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB; -def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), - "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, OpSize; -def XADD8 : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), - "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; - -def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), - "lock xchg{l}\t{$val, $ptr|$ptr, $val}", - [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK; -def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), - "lock xchg{w}\t{$val, $ptr|$ptr, $val}", - [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, - OpSize, LOCK; -def LXCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), - "lock xchg{b}\t{$val, $ptr|$ptr, $val}", - [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK; -def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val), - "xchg{l}\t{$val, $ptr|$ptr, $val}", []>; -def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val), - "xchg{w}\t{$val, $ptr|$ptr, $val}", []>, OpSize; -def XCHG8 : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val), - "xchg{b}\t{$val, $ptr|$ptr, $val}", []>; } //===----------------------------------------------------------------------===//