From: Caesar Wang <wxt@rock-chips.com>
Date: Thu, 7 Jul 2016 00:52:34 +0000 (+0800)
Subject: arm64: dts: rockchip: sync the upstream power domain for rk3399
X-Git-Tag: firefly_0821_release~2200
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7ee13c9f89a5e2daea67de3b3b942b4c1ebf3386;p=firefly-linux-kernel-4.4.55.git

arm64: dts: rockchip: sync the upstream power domain for rk3399

This patch updates the power domain node to sync upstream.
As Heiko landed on [0].

[0]:
https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/
commit/?id=6d3cdbf1c219f9817290903e9d1e8de7462a7b54

Change-Id: Ifbf641965d6f66d0f8a941a1162667ac96709847
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2461680b80b3..0667430c6166 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -795,144 +795,173 @@
 		status = "disabled";
 	};
 
-	qos_gpu: qos_gpu@ffae0000 {
+	qos_hdcp: qos@ffa90000 {
 		compatible = "syscon";
-		reg = <0x0 0xffae0000 0x0 0x20>;
+		reg = <0x0 0xffa90000 0x0 0x20>;
 	};
-	qos_video_m0: qos_video_m0@ffab8000 {
+
+	qos_iep: qos@ffa98000 {
 		compatible = "syscon";
-		reg = <0x0 0xffab8000 0x0 0x20>;
+		reg = <0x0 0xffa98000 0x0 0x20>;
 	};
-	qos_video_m1_r: qos_video_m1_r@ffac0000 {
+
+	qos_isp0_m0: qos@ffaa0000 {
 		compatible = "syscon";
-		reg = <0x0 0xffac0000 0x0 0x20>;
+		reg = <0x0 0xffaa0000 0x0 0x20>;
 	};
-	qos_video_m1_w: qos_video_m1_w@ffac0080 {
+
+	qos_isp0_m1: qos@ffaa0080 {
 		compatible = "syscon";
-		reg = <0x0 0xffac0080 0x0 0x20>;
+		reg = <0x0 0xffaa0080 0x0 0x20>;
 	};
-	qos_rga_r: qos_rga_r@ffab0000 {
+
+	qos_isp1_m0: qos@ffaa8000 {
 		compatible = "syscon";
-		reg = <0x0 0xffab0000 0x0 0x20>;
+		reg = <0x0 0xffaa8000 0x0 0x20>;
 	};
-	qos_rga_w: qos_rga_w@ffab0080 {
+
+	qos_isp1_m1: qos@ffaa8080 {
 		compatible = "syscon";
-		reg = <0x0 0xffab0080 0x0 0x20>;
+		reg = <0x0 0xffaa8080 0x0 0x20>;
 	};
-	qos_iep: qos_iep@ffa98000 {
+
+	qos_rga_r: qos@ffab0000 {
 		compatible = "syscon";
-		reg = <0x0 0xffa98000 0x0 0x20>;
+		reg = <0x0 0xffab0000 0x0 0x20>;
 	};
-	qos_vop_big_r: qos_vop_big_r@ffac8000 {
+
+	qos_rga_w: qos@ffab0080 {
 		compatible = "syscon";
-		reg = <0x0 0xffac8000 0x0 0x20>;
+		reg = <0x0 0xffab0080 0x0 0x20>;
 	};
-	qos_vop_big_w: qos_vop_big_w@ffac8080 {
+
+	qos_video_m0: qos@ffab8000 {
 		compatible = "syscon";
-		reg = <0x0 0xffac8080 0x0 0x20>;
+		reg = <0x0 0xffab8000 0x0 0x20>;
 	};
-	qos_vop_little: qos_vop_little@ffad0000 {
+
+	qos_video_m1_r: qos@ffac0000 {
 		compatible = "syscon";
-		reg = <0x0 0xffad0000 0x0 0x20>;
+		reg = <0x0 0xffac0000 0x0 0x20>;
 	};
-	qos_isp0_m0: qos_isp0_m0@ffaa0000 {
+
+	qos_video_m1_w: qos@ffac0080 {
 		compatible = "syscon";
-		reg = <0x0 0xffaa0000 0x0 0x20>;
+		reg = <0x0 0xffac0080 0x0 0x20>;
 	};
-	qos_isp0_m1: qos_isp0_m1@ffaa0080 {
+
+	qos_vop_big_r: qos@ffac8000 {
 		compatible = "syscon";
-		reg = <0x0 0xffaa0080 0x0 0x20>;
+		reg = <0x0 0xffac8000 0x0 0x20>;
 	};
-	qos_isp1_m0: qos_isp1_m0@ffaa8000 {
+
+	qos_vop_big_w: qos@ffac8080 {
 		compatible = "syscon";
-		reg = <0x0 0xffaa8000 0x0 0x20>;
+		reg = <0x0 0xffac8080 0x0 0x20>;
 	};
-	qos_isp1_m1: qos_isp1_m1@ffaa8080 {
+
+	qos_vop_little: qos@ffad0000 {
 		compatible = "syscon";
-		reg = <0x0 0xffaa8080 0x0 0x20>;
+		reg = <0x0 0xffad0000 0x0 0x20>;
 	};
-	qos_hdcp: qos_hdcp@ffa90000 {
+
+	qos_gpu: qos@ffae0000 {
 		compatible = "syscon";
-		reg = <0x0 0xffa90000 0x0 0x20>;
+		reg = <0x0 0xffae0000 0x0 0x20>;
 	};
 
 	pmu: power-management@ff310000 {
 		compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 		reg = <0x0 0xff310000 0x0 0x1000>;
 
+		/*
+		 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
+		 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
+		 * Some of the power domains are grouped together for every
+		 * voltage domain.
+		 * The detail contents as below.
+		 */
 		power: power-controller {
-			status = "okay";
 			compatible = "rockchip,rk3399-power-controller";
 			#power-domain-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-
-			pd_vdu {
-				reg = <RK3399_PD_VDU>;
-				clocks = <&cru ACLK_VDU>,
-					 <&cru HCLK_VDU>;
-				pm_qos = <&qos_video_m1_r>,
-					 <&qos_video_m1_w>;
-			};
-			pd_vcodec {
-				reg = <RK3399_PD_VCODEC>;
-				clocks = <&cru ACLK_VCODEC>,
-					 <&cru HCLK_VCODEC>;
-				pm_qos = <&qos_video_m0>;
-			};
-			pd_iep {
+			/* These power domains are grouped by VD_CENTER */
+			pd_iep@RK3399_PD_IEP {
 				reg = <RK3399_PD_IEP>;
 				clocks = <&cru ACLK_IEP>,
 					 <&cru HCLK_IEP>;
 				pm_qos = <&qos_iep>;
 			};
-			pd_rga {
+			pd_rga@RK3399_PD_RGA {
 				reg = <RK3399_PD_RGA>;
 				clocks = <&cru ACLK_RGA>,
 					 <&cru HCLK_RGA>;
 				pm_qos = <&qos_rga_r>,
 					 <&qos_rga_w>;
 			};
-			pd_vio {
+			pd_vcodec@RK3399_PD_VCODEC {
+				reg = <RK3399_PD_VCODEC>;
+				clocks = <&cru ACLK_VCODEC>,
+					 <&cru HCLK_VCODEC>;
+				pm_qos = <&qos_video_m0>;
+			};
+			pd_vdu@RK3399_PD_VDU {
+				reg = <RK3399_PD_VDU>;
+				clocks = <&cru ACLK_VDU>,
+					 <&cru HCLK_VDU>;
+				pm_qos = <&qos_video_m1_r>,
+					 <&qos_video_m1_w>;
+			};
+
+			/* These power domains are grouped by VD_GPU */
+			pd_gpu@RK3399_PD_GPU {
+				reg = <RK3399_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+				pm_qos = <&qos_gpu>;
+			};
+
+			/* These power domains are grouped by VD_LOGIC */
+			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				pd_isp0 {
+				pd_hdcp@RK3399_PD_HDCP {
+					reg = <RK3399_PD_HDCP>;
+					clocks = <&cru ACLK_HDCP>,
+						 <&cru HCLK_HDCP>,
+						 <&cru PCLK_HDCP>;
+					pm_qos = <&qos_hdcp>;
+				};
+				pd_isp0@RK3399_PD_ISP0 {
 					reg = <RK3399_PD_ISP0>;
 					clocks = <&cru ACLK_ISP0>,
 						 <&cru HCLK_ISP0>;
 					pm_qos = <&qos_isp0_m0>,
 						 <&qos_isp0_m1>;
 				};
-				pd_isp1 {
+				pd_isp1@RK3399_PD_ISP1 {
 					reg = <RK3399_PD_ISP1>;
 					clocks = <&cru ACLK_ISP1>,
 						 <&cru HCLK_ISP1>;
 					pm_qos = <&qos_isp1_m0>,
 						 <&qos_isp1_m1>;
 				};
-				pd_hdcp {
-					reg = <RK3399_PD_HDCP>;
-					clocks = <&cru ACLK_HDCP>,
-						 <&cru HCLK_HDCP>,
-						 <&cru PCLK_HDCP>;
-					pm_qos = <&qos_hdcp>;
-				};
-				pd_vo {
+				pd_vo@RK3399_PD_VO {
 					reg = <RK3399_PD_VO>;
 					#address-cells = <1>;
 					#size-cells = <0>;
 
-					pd_vopb {
+					pd_vopb@RK3399_PD_VOPB {
 						reg = <RK3399_PD_VOPB>;
 						clocks = <&cru ACLK_VOP0>,
 							 <&cru HCLK_VOP0>;
 						pm_qos = <&qos_vop_big_r>,
 							 <&qos_vop_big_w>;
 					};
-					pd_vopl {
+					pd_vopl@RK3399_PD_VOPL {
 						reg = <RK3399_PD_VOPL>;
 						clocks = <&cru ACLK_VOP1>,
 							 <&cru HCLK_VOP1>;
@@ -940,11 +969,6 @@
 					};
 				};
 			};
-			pd_gpu {
-				reg = <RK3399_PD_GPU>;
-				clocks = <&cru ACLK_GPU>;
-				pm_qos = <&qos_gpu>;
-			};
 		};
 	};