From: Nadav Rotem Date: Wed, 18 Jan 2012 08:33:18 +0000 (+0000) Subject: Fix a bug in the type-legalization of vector integers. When we bitcast one vector... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=819026f2f8b13ac7f6051727fce54b95868c3d85;p=oota-llvm.git Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5c56e474b3d..ee5e1a11548 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -249,8 +249,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); } case TargetLowering::TypeWidenVector: - if (NOutVT.bitsEq(NInVT)) - // The input is widened to the same size. Convert to the widened value. + // The input is widened to the same size. Convert to the widened value. + // Make sure that the outgoing value is not a vector, because this would + // make us bitcast between two vectors which are legalized in different ways. + if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); } diff --git a/test/CodeGen/X86/2012-01-18-vbitcast.ll b/test/CodeGen/X86/2012-01-18-vbitcast.ll new file mode 100644 index 00000000000..8a3ccc8dfda --- /dev/null +++ b/test/CodeGen/X86/2012-01-18-vbitcast.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s + +;CHECK: vcast +define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) { +;CHECK: pshufd +;CHECK: pshufd + %af = bitcast <2 x float> %a to <2 x i32> + %bf = bitcast <2 x float> %b to <2 x i32> + %x = sub <2 x i32> %af, %bf +;CHECK: psubq + ret <2 x i32> %x +;CHECK: ret +} +