From: Robin Morisset <morisset@google.com>
Date: Tue, 23 Sep 2014 18:33:21 +0000 (+0000)
Subject: Just add a fixme about a possibly faster implementation of some atomic loads on some... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8439e5e4c465907386e1a6c02be6d8cb17226519;p=oota-llvm.git

Just add a fixme about a possibly faster implementation of some atomic loads on some ARM processors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218326 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index ca6b614ce2e..97b62264462 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -11086,6 +11086,9 @@ bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
 // are doomed anyway, so defer to the default libcall and blame the OS when
 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
 // anything for those.
+// FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
+// guarantee, see DDI0406C ARM architecture reference manual,
+// sections A8.8.72-74 LDRD)
 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
   unsigned Size = LI->getType()->getPrimitiveSizeInBits();
   return (Size == 64) && !Subtarget->isMClass();