From: James Molloy <james.molloy@arm.com>
Date: Mon, 12 Oct 2015 12:49:59 +0000 (+0000)
Subject: [ARM] Mark Swift MISched model as incomplete
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=85125fcdd66f8745b5388a8405f9a5dba6f03c96;p=oota-llvm.git

[ARM] Mark Swift MISched model as incomplete

The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM
target.

Patch by Christof Douma!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250033 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td
index 6f5740fd130..3ad7730228e 100644
--- a/lib/Target/ARM/ARMScheduleSwift.td
+++ b/lib/Target/ARM/ARMScheduleSwift.td
@@ -43,6 +43,7 @@ def SwiftModel : SchedMachineModel {
   let MicroOpBufferSize = 45; // Based on NEON renamed registers.
   let LoadLatency = 3;
   let MispredictPenalty = 14; // A branch direction mispredict.
+  let CompleteModel = 0;      // FIXME: Remove if all instructions are covered.
 }
 
 // Swift predicates.