From: Nicolin Chen Date: Mon, 4 Aug 2014 07:07:25 +0000 (+0800) Subject: ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode X-Git-Tag: firefly_0821_release~176^2~2610^2~90^2~5^3~2 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=855675f6e6a65688a7f4cf45b9b5a98cf6c6f5c3;p=firefly-linux-kernel-4.4.55.git ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode There is one design rule according to SAI's reference manual: If the transmitter bit clock and frame sync are to be used by both transmitter and receiver, the transmitter must be configured for asynchronous operation and the receiver for synchronous operation. And SYNC of TCR2 is a 2-width control bit: 00 Asynchronous mode. 01 Synchronous with receiver. 10 Synchronous with another SAI transmitter. 11 Synchronous with another SAI receiver. So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC bit of RCR2 to 0x1 (Synchronous with transmitter). Signed-off-by: Nicolin Chen Signed-off-by: Mark Brown --- diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 4c9e71c2f52a..60fe7c77ba22 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -334,8 +334,7 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. */ - regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, - sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); + regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0); regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);