From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 14:22:46 +0000 (+0000)
Subject: Proper FP extloads
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=85c5c3f138257eb8db8f7afc9c0543ee48d88201;p=oota-llvm.git

Proper FP extloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76028 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 83afcf404aa..01ecf4fae90 100644
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -65,13 +65,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
 
-  setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Promote);
-  setLoadExtAction(ISD::EXTLOAD,  MVT::f32, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::f32, Expand);
 
-  setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Promote);
-  setLoadExtAction(ISD::EXTLOAD,  MVT::f64, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
+  setLoadExtAction(ISD::EXTLOAD,  MVT::f64, Expand);
 
   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
   setSchedulingPreference(SchedulingForLatency);
diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td
index 1c1b0ebb353..b54cd26c6d2 100644
--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@@ -167,10 +167,12 @@ def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
                          "ledbr\t{$dst, $src}",
                          [(set FP32:$dst, (fround FP64:$src))]>;
 
-// FIXME: memory variant
 def FEXT32r64   : Pseudo<(outs FP64:$dst), (ins FP32:$src),
                          "ldebr\t{$dst, $src}",
                          [(set FP64:$dst, (fextend FP32:$src))]>;
+def FEXT32m64   : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
+                         "ldeb\t{$dst, $src}",
+                         [(set FP64:$dst, (fextend (load rriaddr:$src)))]>;
 
 let Defs = [PSW] in {
 def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),