From: Chris Lattner <sabre@nondot.org>
Date: Sat, 15 Oct 2005 22:18:08 +0000 (+0000)
Subject: Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=85d63bbff740d23fae631ec1ecf5c7603e4b321d;p=oota-llvm.git

Add a case we were missing that was causing us to fail CodeGen/PowerPC/rlwinm.ll:test3


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23755 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 879dc5b36f7..35c981d7f3d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -803,6 +803,20 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
     WorkList.push_back(ANDNode.Val);
     return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
   }
+  // fold (and (sra)) -> (and (srl)) when possible.
+  if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
+    if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+      // If the RHS of the AND has zeros where the sign bits of the SRA will
+      // land, turn the SRA into an SRL.
+      if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
+                            (~0ULL>>(64-OpSizeInBits)), TLI)) {
+        WorkList.push_back(N);
+        CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
+                                      N0.getOperand(1)));
+        return SDOperand();
+      }
+    }
+      
   // fold (zext_inreg (extload x)) -> (zextload x)
   if (N0.getOpcode() == ISD::EXTLOAD) {
     MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();