From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 21 Dec 2005 20:20:49 +0000 (+0000)
Subject: Allows instructions which no explicit operands. e.g. X86 RET which has but
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=87bddeb2afeaa8cebe43a216430375afec8c16d3;p=oota-llvm.git

Allows instructions which no explicit operands. e.g. X86 RET which has but
an implicit flag operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24916 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index be8fb75b43a..140c8f2bf12 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -1124,23 +1124,22 @@ void DAGISelEmitter::ParseInstructions() {
       std::vector<Record*> Operands;
       
       CodeGenInstruction &InstInfo =Target.getInstruction(Instrs[i]->getName());
-      
-      // Doesn't even define a result?
-      if (InstInfo.OperandList.size() == 0)
-        continue;
 
+      // Note: Removed if (InstInfo.OperandList.size() == 0) continue;
+      // It's possible for some instruction, e.g. RET for X86 that only has an
+      // implicit flag operand.
       // FIXME: temporary hack...
       if (InstInfo.isReturn || InstInfo.isBranch || InstInfo.isCall ||
           InstInfo.isStore) {
         // These produce no results
-        for (unsigned j = 0, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 0, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       } else {
         // Assume the first operand is the result.
         Results.push_back(InstInfo.OperandList[0].Rec);
       
         // The rest are inputs.
-        for (unsigned j = 1, e = InstInfo.OperandList.size(); j != e; ++j)
+        for (unsigned j = 1, e = InstInfo.OperandList.size(); j < e; ++j)
           Operands.push_back(InstInfo.OperandList[j].Rec);
       }