From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 26 Sep 2014 17:55:09 +0000 (+0000)
Subject: R600/SI: Add a note about the order of the operands to div_scale
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=88416c337b6562ca7fe21ebf1374f6747c082e9b;p=oota-llvm.git

R600/SI: Add a note about the order of the operands to div_scale

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218534 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 29d3fc38e57..32bab66aeed 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -825,6 +825,12 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
       // first parameter must be the same as the first instruction.
       SDValue Numerator = Op.getOperand(1);
       SDValue Denominator = Op.getOperand(2);
+
+      // Note this order is opposite of the machine instruction's operations,
+      // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
+      // intrinsic has the numerator as the first operand to match a normal
+      // division operation.
+
       SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
 
       return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,