From: dkl Date: Tue, 8 Jul 2014 06:24:17 +0000 (+0800) Subject: reset: rk3036: add rk3036 reset-controller support X-Git-Tag: firefly_0821_release~4916^2~286 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8929905cb93e56f3ec03cfd5db86e67498a20fed;p=firefly-linux-kernel-4.4.55.git reset: rk3036: add rk3036 reset-controller support --- diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 020d05a7c3b5..43130a8d3521 100755 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -92,6 +92,13 @@ }; }; + reset: reset@20000110{ + compatible = "rockchip,reset"; + reg = <0x20000110 0x24>; + rockchip,reset-flag = ; + #reset-cells = <1>; + }; + nandc: nandc@10500000 { compatible = "rockchip,rk-nandc"; reg = <0x10500000 0x4000>; diff --git a/include/dt-bindings/clock/rockchip,rk3036.h b/include/dt-bindings/clock/rockchip,rk3036.h index ec2ef200ff2e..019550c7d0c1 100644 --- a/include/dt-bindings/clock/rockchip,rk3036.h +++ b/include/dt-bindings/clock/rockchip,rk3036.h @@ -9,4 +9,147 @@ #define RK3036_GPLL_ID 2 #define RK3036_END_PLL_ID 3 +/* reset id */ +#define RK3036_RST_CORE0 0 +#define RK3036_RST_CORE1 1 +#define RK3036_RST_0RES2 2 +#define RK3036_RST_0RES3 3 +#define RK3036_RST_CORE0_DBG 4 +#define RK3036_RST_CORE1_DBG 5 +#define RK3036_RST_0RES6 6 +#define RK3036_RST_0RES7 7 +#define RK3036_RST_CORE0_POR 8 +#define RK3036_RST_CORE1_POR 9 +#define RK3036_RST_0RES10 10 +#define RK3036_RST_0RES11 11 +#define RK3036_RST_L2C 12 +#define RK3036_RST_TOPDBG 13 +#define RK3036_RST_STRC_SYS_A 14 +#define RK3036_RST_PD_CORE_NIU 15 + +#define RK3036_RST_TIMER2 16 +#define RK3036_RST_CPUSYS_H 17 +#define RK3036_RST_1RES2 18 +#define RK3036_RST_AHB2APB_H 19 +#define RK3036_RST_TIMER3 20 +#define RK3036_RST_INTMEM 21 +#define RK3036_RST_ROM 22 +#define RK3036_RST_PERI_NIU 23 +#define RK3036_RST_I2S 24 +#define RK3036_RST_DDR_PLL 25 +#define RK3036_RST_GPU_DLL 26 +#define RK3036_RST_TIMER0 27 +#define RK3036_RST_TIMER1 28 +#define RK3036_RST_CORE_DLL 29 +#define RK3036_RST_EFUSE_P 30 +#define RK3036_RST_ACODEC_P 31 + +#define RK3036_RST_GPIO0 32 +#define RK3036_RST_GPIO1 33 +#define RK3036_RST_GPIO2 34 +#define RK3036_RST_2RES3 35 +#define RK3036_RST_2RES4 36 +#define RK3036_RST_2RES5 37 +#define RK3036_RST_2RES6 38 +#define RK3036_RST_UART0 39 +#define RK3036_RST_UART1 40 +#define RK3036_RST_UART2 41 +#define RK3036_RST_2RES10 42 +#define RK3036_RST_I2C0 43 +#define RK3036_RST_I2C1 44 +#define RK3036_RST_I2C2 45 +#define RK3036_RST_2RES14 46 +#define RK3036_RST_SFC 47 + +#define RK3036_RST_PWM0 48 +#define RK3036_RST_3RES1 49 +#define RK3036_RST_3RES2 50 +#define RK3036_RST_DAP 51 +#define RK3036_RST_DAP_SYS 52 +#define RK3036_RST_3RES5 53 +#define RK3036_RST_3RES6 54 +#define RK3036_RST_GRF 55 +#define RK3036_RST_3RES8 56 +#define RK3036_RST_PERIPHSYS_A 57 +#define RK3036_RST_PERIPHSYS_H 58 +#define RK3036_RST_PERIPHSYS_P 59 +#define RK3036_RST_3RES12 60 +#define RK3036_RST_CPU_PERI 61 +#define RK3036_RST_EMEM_PERI 62 +#define RK3036_RST_USB_PERI 63 + +#define RK3036_RST_DMA2 64 +#define RK3036_RST_4RES1 65 +#define RK3036_RST_MAC 66 +#define RK3036_RST_4RES3 67 +#define RK3036_RST_NANDC 68 +#define RK3036_RST_USBOTG0 69 +#define RK3036_RST_4RES6 70 +#define RK3036_RST_OTGC0 71 +#define RK3036_RST_USBOTG1 72 +#define RK3036_RST_4RES9 73 +#define RK3036_RST_OTGC1 74 +#define RK3036_RST_4RES11 75 +#define RK3036_RST_4RES12 76 +#define RK3036_RST_4RES13 77 +#define RK3036_RST_4RES14 78 +#define RK3036_RST_DDRMSCH 79 + +#define RK3036_RST_5RES0 80 +#define RK3036_RST_MMC0 81 +#define RK3036_RST_SDIO 82 +#define RK3036_RST_EMMC 83 +#define RK3036_RST_SPI0 84 +#define RK3036_RST_5RES5 85 +#define RK3036_RST_WDT 86 +#define RK3036_RST_5RES7 87 +#define RK3036_RST_DDRPHY 88 +#define RK3036_RST_DDRPHY_P 89 +#define RK3036_RST_DDRCTRL 90 +#define RK3036_RST_DDRCTRL_P 91 +#define RK3036_RST_5RES12 92 +#define RK3036_RST_5RES13 93 +#define RK3036_RST_5RES14 94 +#define RK3036_RST_5RES15 95 + +#define RK3036_RST_HDMI_P 96 +#define RK3036_RST_6RES1 97 +#define RK3036_RST_6RES2 98 +#define RK3036_RST_VIO_BUS_H 99 +#define RK3036_RST_6RES4 100 +#define RK3036_RST_6RES5 101 +#define RK3036_RST_6RES6 102 +#define RK3036_RST_UTMI0 103 +#define RK3036_RST_UTMI1 104 +#define RK3036_RST_USBPOR 105 +#define RK3036_RST_6RES10 106 +#define RK3036_RST_6RES11 107 +#define RK3036_RST_6RES12 108 +#define RK3036_RST_6RES13 109 +#define RK3036_RST_6RES14 110 +#define RK3036_RST_6RES15 111 + +#define RK3036_RST_VCODEC_A 112 +#define RK3036_RST_VCODEC_H 113 +#define RK3036_RST_VIO1_A 114 +#define RK3036_RST_HEVC 115 +#define RK3036_RST_VCODEC_NIU_A 116 +#define RK3036_RST_LCDC1_A 117 +#define RK3036_RST_LCDC1_H 118 +#define RK3036_RST_LCDC1_D 119 +#define RK3036_RST_GPU 120 +#define RK3036_RST_7RES9 121 +#define RK3036_RST_GPU_NIU_A 122 +#define RK3036_RST_7RES11 123 +#define RK3036_RST_7RES12 124 +#define RK3036_RST_7RES13 125 +#define RK3036_RST_7RES14 126 +#define RK3036_RST_7RES15 127 + +#define RK3036_RST_8RES0 128 +#define RK3036_RST_8RES1 129 +#define RK3036_RST_8RES2 130 +#define RK3036_RST_DBG_P 131 +/* con8[15:4] is reserved */ + #endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_RK3036_H */