From: Chris Lattner <sabre@nondot.org>
Date: Wed, 15 Oct 2008 03:52:54 +0000 (+0000)
Subject: factor some more BuildMI's in X86SelectCmp
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8aeeeb9d24fe36dab5d193174487f05a1fa640d3;p=oota-llvm.git

factor some more BuildMI's in X86SelectCmp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57545 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 44657ecd1c8..be5c937244f 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -546,7 +546,7 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
 
   unsigned ResultReg = createResultReg(&X86::GR8RegClass);
   unsigned SetCCOpc;
-  
+  bool SwapArgs;  // false -> compare Op0, Op1.  true -> compare Op1, Op0.
   switch (CI->getPredicate()) {
   case CmpInst::FCMP_OEQ: {
     unsigned EReg = createResultReg(&X86::GR8RegClass);
@@ -568,101 +568,39 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
     UpdateValueMap(I, ResultReg);
     return true;
   }
-  case CmpInst::FCMP_OGT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETAr;
-    break;
-  case CmpInst::FCMP_OGE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETAEr;
-    break;
-  case CmpInst::FCMP_OLT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
-    SetCCOpc = X86::SETAr;
-    break;
-  case CmpInst::FCMP_OLE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
-    SetCCOpc = X86::SETAEr;
-    break;
-  case CmpInst::FCMP_ONE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETNEr;
-    break;
-  case CmpInst::FCMP_ORD:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETNPr;
-    break;
-  case CmpInst::FCMP_UNO:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETPr;
-    break;
-  case CmpInst::FCMP_UEQ:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETEr;
-    break;
-  case CmpInst::FCMP_UGT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
-    SetCCOpc = X86::SETBr;
-    break;
-  case CmpInst::FCMP_UGE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
-    SetCCOpc = X86::SETBEr;
-    break;
-  case CmpInst::FCMP_ULT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETBr;
-    break;
-  case CmpInst::FCMP_ULE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETBEr;
-    break;
-  case CmpInst::ICMP_EQ:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETEr;
-    break;
-  case CmpInst::ICMP_NE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETNEr;
-    break;
-  case CmpInst::ICMP_UGT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETAr;
-    break;
-  case CmpInst::ICMP_UGE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETAEr;
-    break;
-  case CmpInst::ICMP_ULT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETBr;
-    break;
-  case CmpInst::ICMP_ULE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETBEr;
-    break;
-  case CmpInst::ICMP_SGT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETGr;
-    break;
-  case CmpInst::ICMP_SGE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETGEr;
-    break;
-  case CmpInst::ICMP_SLT:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETLr;
-    break;
-  case CmpInst::ICMP_SLE:
-    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
-    SetCCOpc = X86::SETLEr;
-    break;
+  case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr;  break;
+  case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
+  case CmpInst::FCMP_OLT: SwapArgs = true;  SetCCOpc = X86::SETAr;  break;
+  case CmpInst::FCMP_OLE: SwapArgs = true;  SetCCOpc = X86::SETAEr; break;
+  case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
+  case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
+  case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr;  break;
+  case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr;  break;
+  case CmpInst::FCMP_UGT: SwapArgs = true;  SetCCOpc = X86::SETBr;  break;
+  case CmpInst::FCMP_UGE: SwapArgs = true;  SetCCOpc = X86::SETBEr; break;
+  case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr;  break;
+  case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
+  
+  case CmpInst::ICMP_EQ:  SwapArgs = false; SetCCOpc = X86::SETEr;  break;
+  case CmpInst::ICMP_NE:  SwapArgs = false; SetCCOpc = X86::SETNEr; break;
+  case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr;  break;
+  case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
+  case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr;  break;
+  case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
+  case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr;  break;
+  case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
+  case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr;  break;
+  case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
   default:
     return false;
   }
 
-  if (SetCCOpc)
-    BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
-  
+  if (SwapArgs)
+    BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
+  else
+    BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
+
+  BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
   UpdateValueMap(I, ResultReg);
   return true;
 }