From: Matthias Braun <matze@braunis.de>
Date: Wed, 18 Mar 2015 17:56:09 +0000 (+0000)
Subject: TableGen: Fix register class lane masks being too conservative.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8b41add6ca68108ddee98b99c5213215ca82eba9;p=oota-llvm.git

TableGen: Fix register class lane masks being too conservative.

When calculating the lanemask of a register class we have to include the
masks of subregisters supported by any of the class members, not just
the ones supported by all class members.

This fixes problems when coalescing towards a subclass with additional
subregisters available.

The attached testcase works fine as is, but does crash if you enable
subregister liveness on x86 without this change applied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232652 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/coalescer-subreg.ll b/test/CodeGen/X86/coalescer-subreg.ll
new file mode 100644
index 00000000000..be80dff779c
--- /dev/null
+++ b/test/CodeGen/X86/coalescer-subreg.ll
@@ -0,0 +1,29 @@
+; RUN: llc -o - %s -verify-machineinstrs
+; This used to crash when coalescing a regclass like GR16 which did not support
+; the sub_8bit_hi subregister with a class like GR16_ABCD that did.
+target triple = "x86_64-apple-macosx10.10.0"
+
+define void @test() #0 {
+entry:
+  br i1 undef, label %loop, label %for.end597
+
+loop:
+  %0 = load i16, i16* null, align 4
+  %1 = load i16, i16* undef, align 4
+  %or1 = or i16 %1, %0
+  %or2 = trunc i16 %or1 to i8
+  store i8 %or2, i8* undef, align 4
+  %2 = or i16 %1, %0
+  %or3 = lshr i16 %2, 8
+  %or4 = trunc i16 %or3 to i8
+  store i8 %or4, i8* undef, align 1
+  %3 = load i32, i32* undef, align 4
+  %4 = load i32, i32* undef, align 4
+  %or5 = or i32 %4, %3
+  store i32 %or5, i32* undef, align 4
+  store i32 0, i32* undef, align 4
+  br label %loop
+
+for.end597:
+  ret void
+}
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 56ac6e0884e..cd4075b0e75 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -1260,7 +1260,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
   for (auto &RegClass : RegClasses) {
     unsigned LaneMask = 0;
     for (const auto &SubRegIndex : SubRegIndices) {
-      if (RegClass.getSubClassWithSubReg(&SubRegIndex) != &RegClass)
+      if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
         continue;
       LaneMask |= SubRegIndex.LaneMask;
     }