From: Jakob Stoklund Olesen Date: Wed, 28 Mar 2012 23:54:28 +0000 (+0000) Subject: Enable machine code verification in the entire code generator. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8b4c502098d8a8aee52f2251db5614d9d26c83e2;p=oota-llvm.git Enable machine code verification in the entire code generator. Some targets still mess up the liveness information, but that isn't verified after MRI->invalidateLiveness(). The verifier can still check other useful things like register classes and CFG, so it should be enabled after all passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153615 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index d6ca148ea02..3b381998588 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -223,11 +223,6 @@ protected: /// regalloc pass. FunctionPass *createRegAllocPass(bool Optimized); - /// printNoVerify - Add a pass to dump the machine function, if debugging is - /// enabled. - /// - void printNoVerify(const char *Banner) const; - /// printAndVerify - Add a pass to dump then verify the machine function, if /// those steps are enabled. /// diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index 4a25af02f05..53d1fcf7377 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -272,11 +272,6 @@ AnalysisID TargetPassConfig::addPass(char &ID) { return FinalID; } -void TargetPassConfig::printNoVerify(const char *Banner) const { - if (TM->shouldPrintMachineCode()) - PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); -} - void TargetPassConfig::printAndVerify(const char *Banner) const { if (TM->shouldPrintMachineCode()) PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); @@ -403,7 +398,7 @@ void TargetPassConfig::addMachinePasses() { // Second pass scheduler. if (getOptLevel() != CodeGenOpt::None) { addPass(PostRASchedulerID); - printNoVerify("After PostRAScheduler"); + printAndVerify("After PostRAScheduler"); } // GC @@ -416,7 +411,7 @@ void TargetPassConfig::addMachinePasses() { addBlockPlacement(); if (addPreEmitPass()) - printNoVerify("After PreEmit passes"); + printAndVerify("After PreEmit passes"); } /// Add passes that optimize machine instructions in SSA form. @@ -628,6 +623,6 @@ void TargetPassConfig::addBlockPlacement() { if (EnableBlockPlacementStats) addPass(MachineBlockPlacementStatsID); - printNoVerify("After machine block placement."); + printAndVerify("After machine block placement."); } } diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp index 57bbe0bd3fe..c55a658dc37 100644 --- a/lib/Target/PTX/PTXTargetMachine.cpp +++ b/lib/Target/PTX/PTXTargetMachine.cpp @@ -152,10 +152,10 @@ bool PTXPassConfig::addPostRegAlloc() { /// Add passes that optimize machine instructions after register allocation. void PTXPassConfig::addMachineLateOptimization() { if (addPass(BranchFolderPassID) != &NoPassID) - printNoVerify("After BranchFolding"); + printAndVerify("After BranchFolding"); if (addPass(TailDuplicateID) != &NoPassID) - printNoVerify("After TailDuplicate"); + printAndVerify("After TailDuplicate"); } bool PTXPassConfig::addPreEmitPass() {