From: xubilv Date: Thu, 29 Jun 2017 02:27:55 +0000 (+0800) Subject: clk: rockchip: 3288: dclk will change if cpll initialized X-Git-Tag: release-20171130_firefly~4^2~284 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8d3966e35fb8d92a55ef675320efbbcf457a013e;p=firefly-linux-kernel-4.4.55.git clk: rockchip: 3288: dclk will change if cpll initialized Change-Id: I698437b21c94684af0a7dfbe643794de62edc962 Signed-off-by: xubilv --- diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 5d9ec9c3feb0..7ceee5cf28be 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -209,7 +209,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4), RK3288_MODE_CON, 4, 5, 0, NULL), [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8), - RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), + RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates), [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),