From: WeiYong Bi <bivvy.bi@rock-chips.com>
Date: Wed, 12 Jul 2017 06:19:47 +0000 (+0800)
Subject: drm/rockchip: dsi: Add support for rk3366
X-Git-Tag: release-20171130_firefly~4^2~206
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8e803e4c3413e5e8c68aba905949688d9f8659a3;p=firefly-linux-kernel-4.4.55.git

drm/rockchip: dsi: Add support for rk3366

Change-Id: I9edfea9652d8c56065590ea01480b49f1c432145
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
---

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index e26bfd4d819e..53bd63dec116 100644
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -4,9 +4,11 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
 Required properties:
 - #address-cells: Should be <1>.
 - #size-cells: Should be <0>.
-- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
-  or "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
-  or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
+- compatible: must be one of:
+	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+	"rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
+	"rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
+	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
 - reg: Represent the physical address range of the controller.
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 0d29890235a0..77b879b560dc 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -35,6 +35,9 @@
 #define RK3288_DSI0_SEL_VOP_LIT		BIT(6)
 #define RK3288_DSI1_SEL_VOP_LIT		BIT(9)
 
+#define RK3366_GRF_SOC_CON0		0x0400
+#define RK3366_DSI_SEL_VOP_LIT		BIT(2)
+
 #define RK3399_GRF_SOC_CON19		0x6250
 #define RK3399_DSI0_SEL_VOP_LIT		BIT(0)
 #define RK3399_DSI1_SEL_VOP_LIT		BIT(4)
@@ -1162,6 +1165,19 @@ static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
 	.has_vop_sel = true,
 };
 
+static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
+	.dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
+	.grf_switch_reg = RK3366_GRF_SOC_CON0,
+	.max_data_lanes = 4,
+	.max_bit_rate_per_lane = 1000000000,
+	.has_vop_sel = true,
+};
+
+static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
+	.max_data_lanes = 4,
+	.max_bit_rate_per_lane = 1000000000,
+};
+
 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
 	.dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
 	.dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
@@ -1173,21 +1189,19 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
 	.has_vop_sel = true,
 };
 
-static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
-	.max_data_lanes = 4,
-	.max_bit_rate_per_lane = 1000000000,
-};
-
 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
 	{
 	 .compatible = "rockchip,rk3288-mipi-dsi",
 	 .data = &rk3288_mipi_dsi_drv_data,
-	},{
-	 .compatible = "rockchip,rk3399-mipi-dsi",
-	 .data = &rk3399_mipi_dsi_drv_data,
+	}, {
+	 .compatible = "rockchip,rk3366-mipi-dsi",
+	 .data = &rk3366_mipi_dsi_drv_data,
 	}, {
 	 .compatible = "rockchip,rk3368-mipi-dsi",
 	 .data = &rk3368_mipi_dsi_drv_data,
+	}, {
+	 .compatible = "rockchip,rk3399-mipi-dsi",
+	 .data = &rk3399_mipi_dsi_drv_data,
 	},
 	{ /* sentinel */ }
 };