From: chenxing <chenxing@rock-chips.com>
Date: Sat, 21 Apr 2012 08:33:40 +0000 (+0800)
Subject: rk30: change gpll_clks frequency division, to achieve higher accuracy
X-Git-Tag: firefly_0821_release~9349
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8f1f5c6a6b22f85a1ef005e5a9e17f84a1ed8c90;p=firefly-linux-kernel-4.4.55.git

rk30: change gpll_clks frequency division, to achieve higher accuracy
---

diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index f6332e8207ad..230c6b511c79 100755
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -1044,9 +1044,9 @@ static struct clk codec_pll_clk = {
 
 static const struct pll_clk_set gpll_clks[] = {
 	_PLL_SET_CLKS(148500,	4,	99,	4),
-	_PLL_SET_CLKS(297000,	4,	99,	2),
-	_PLL_SET_CLKS(1188000,	2,	99,	2),
-	_PLL_SET_CLKS(0,		0,	 0,	0),
+	_PLL_SET_CLKS(297000,	2,	99,	4),
+	_PLL_SET_CLKS(1188000,	1,	99,	2),
+	_PLL_SET_CLKS(0,	0,	 0,	0),
 };
 static struct _pll_data gpll_data=SET_PLL_DATA(GPLL_ID,(void *)gpll_clks);
 static struct clk general_pll_clk = {