From: Ville Syrjälä Date: Thu, 27 Feb 2014 12:23:12 +0000 (+0200) Subject: drm/i915: Fix DDI port_clock for VGA output X-Git-Tag: firefly_0821_release~176^2~3773^2~63^2~271 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8f7abfd82246a8d8b5bd1ad3056f3b46345b6b4a;p=firefly-linux-kernel-4.4.55.git drm/i915: Fix DDI port_clock for VGA output On DDI there's no PLL as such to generate the pixel clock for VGA. Instead we derive the pixel clock from the FDI link frequency. So to make .compute_config match what .get_config does, we need to set the port_clock based on the FDI link frequency. Note that we don't even check the port_clock when selecting the PLL for VGA output. We just assume SPLL at 1.35GHz is what we want, and that does match with the asumption of FDI frequency of 2.7Ghz we have in intel_fdi_link_freq(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74955 Signed-off-by: Ville Syrjälä Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 4c1230c737d5..469071db3528 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -262,6 +262,10 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder, if (HAS_PCH_LPT(dev)) pipe_config->pipe_bpp = 24; + /* FDI must always be 2.7 GHz */ + if (HAS_DDI(dev)) + pipe_config->port_clock = 135000 * 2; + return true; }