From: yxj Date: Fri, 21 Mar 2014 07:05:11 +0000 (+0800) Subject: rk32 dp temporarily ok X-Git-Tag: firefly_0821_release~5929 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=8fe56f1777110126622df3bb735f2b200e658cdf;p=firefly-linux-kernel-4.4.55.git rk32 dp temporarily ok --- diff --git a/drivers/video/rockchip/transmitter/rk32_dp.c b/drivers/video/rockchip/transmitter/rk32_dp.c index e9f4cbc9555f..4123be1b0126 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp.c +++ b/drivers/video/rockchip/transmitter/rk32_dp.c @@ -31,20 +31,27 @@ #include #endif -/*#define EDP_BIST_MODE*/ +//#define EDP_BIST_MODE static struct rk32_edp *rk32_edp; static int rk32_edp_init_edp(struct rk32_edp *edp) { struct rk_screen *screen = &edp->screen; u32 val = 0; - + + screen->lcdc_id = 1; if (screen->lcdc_id == 1) /*select lcdc*/ val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16); else val = EDP_SEL_VOP_LIT << 16; writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6); + val = GRF_EDP_REF_CLK_SEL_INTER | + (GRF_EDP_REF_CLK_SEL_INTER << 16); + writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12); + + val = 0x80008000; + writel_relaxed(val, RK_CRU_VIRT + 0x0d0); rk32_edp_reset(edp); rk32_edp_init_refclk(edp); rk32_edp_init_interrupt(edp); @@ -1058,7 +1065,7 @@ static irqreturn_t rk32_edp_isr(int irq, void *arg) { struct rk32_edp *edp = arg; - dev_info(edp->dev, "rk32_edp_isr\n"); + //dev_info(edp->dev, "rk32_edp_isr\n"); return IRQ_HANDLED; } @@ -1079,32 +1086,31 @@ edp_phy_init: rk32_edp_init_edp(edp); - - ret = rk32_edp_handle_edid(edp); + /*ret = rk32_edp_handle_edid(edp); if (ret) { dev_err(edp->dev, "unable to handle edid\n"); - goto out; + //goto out; } ret = rk32_edp_enable_scramble(edp, 0); if (ret) { dev_err(edp->dev, "unable to set scramble\n"); - goto out; + //goto out; } ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0); if (ret) { dev_err(edp->dev, "unable to set enhanced mode\n"); - goto out; + //goto out; } - rk32_edp_enable_enhanced_mode(edp, 0); + rk32_edp_enable_enhanced_mode(edp, 0);*/ /* Link Training */ ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS); if (ret) { dev_err(edp->dev, "link train failed\n"); - goto out; + //goto out; } rk32_edp_set_lane_count(edp, edp->video_info.lane_count); @@ -1117,10 +1123,9 @@ edp_phy_init: ret = rk32_edp_config_video(edp, &edp->video_info); if (ret) { dev_err(edp->dev, "unable to config video\n"); - goto out; + //goto out; } #endif - return 0; out: @@ -1131,7 +1136,6 @@ out: } dev_err(edp->dev, "DP LT exceeds max retry count"); - return ret; } @@ -1185,7 +1189,7 @@ static int rk32_edp_probe(struct platform_device *pdev) edp->video_info.ycbcr_coeff = COLOR_YCBCR601; edp->video_info.color_depth = COLOR_8; - edp->video_info.link_rate = LINK_RATE_2_70GBPS; + edp->video_info.link_rate = LINK_RATE_1_62GBPS; edp->video_info.lane_count = LANE_CNT4; rk_fb_get_prmry_screen(&edp->screen); if (edp->screen.type != SCREEN_EDP) { @@ -1220,7 +1224,7 @@ static int rk32_edp_probe(struct platform_device *pdev) return PTR_ERR(edp->pclk); } - edp->irq = platform_get_irq(pdev, 0); + /*edp->irq = platform_get_irq(pdev, 0); if (edp->irq < 0) { dev_err(&pdev->dev, "cannot find IRQ\n"); return edp->irq; @@ -1231,6 +1235,7 @@ static int rk32_edp_probe(struct platform_device *pdev) dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq); return ret; } + disable_irq(edp->irq);*/ rk32_edp = edp; clk_prepare(edp->pclk); clk_prepare(edp->clk_edp); diff --git a/drivers/video/rockchip/transmitter/rk32_dp.h b/drivers/video/rockchip/transmitter/rk32_dp.h index f84757cfc71d..8a3325d8f035 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp.h +++ b/drivers/video/rockchip/transmitter/rk32_dp.h @@ -88,10 +88,20 @@ #define HB_PORCHL_REG 0x84 #define HB_PORCHH_REG 0x88 + +#define SSC_REG 0x104 +#define TX_REG_COMMON 0x114 +#define DP_AUX 0x120 +#define DP_BIAS 0x124 + #define PLL_REG_1 0xfc #define REF_CLK_24M (0x01 << 1) #define REF_CLK_27M (0x0 << 1) +#define PLL_REG_2 0x9e4 +#define PLL_REG_3 0x9e8 +#define PLL_REG_4 0x9ec +#define PLL_REG_5 0xa00 #define DP_PWRDN 0x12c #define PD_INC_BG (0x1 << 7) #define PD_EXP_BG (0x1 << 6) @@ -102,6 +112,8 @@ #define PD_CH1 (0x1 << 1) #define PD_CH0 (0x1 << 0) +#define DP_RESERVE2 0x134 + #define LANE_MAP 0x35C #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) @@ -372,6 +384,7 @@ #define GRF_EDP_MEM_CTL_BY_EDP (1 << 13) #define GRF_EDP_SECURE_EN (1 << 3) #define EDP_SEL_VOP_LIT (1 << 5) +#define GRF_EDP_REF_CLK_SEL_INTER (1 << 4) enum color_coefficient { COLOR_YCBCR601, COLOR_YCBCR709 diff --git a/drivers/video/rockchip/transmitter/rk32_dp_reg.c b/drivers/video/rockchip/transmitter/rk32_dp_reg.c index d8f979b4ea5e..944b00f98e61 100644 --- a/drivers/video/rockchip/transmitter/rk32_dp_reg.c +++ b/drivers/video/rockchip/transmitter/rk32_dp_reg.c @@ -78,6 +78,31 @@ void rk32_edp_init_refclk(struct rk32_edp *edp) val = REF_CLK_24M; writel(val, edp->regs + PLL_REG_1); + + val = 0x95; + writel(val, edp->regs + PLL_REG_2); + + val = 0x40; + writel(val, edp->regs + PLL_REG_3); + + val = 0x58; + writel(val, edp->regs + PLL_REG_4); + + val = 0x22; + writel(val, edp->regs + PLL_REG_5); + + val = 0x19; + writel(val, edp->regs + SSC_REG); + val = 0x87; + writel(val, edp->regs + TX_REG_COMMON); + val = 0x03; + writel(val, edp->regs + DP_AUX); + val = 0x46; + writel(val, edp->regs + DP_BIAS); + val = 0x55; + writel(val, edp->regs + DP_RESERVE2); + + /*val = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; writel(val, edp->regs + ANALOG_CTL_3); @@ -251,8 +276,17 @@ void rk32_edp_init_analog_func(struct rk32_edp *edp) writel(val, edp->regs + DEBUG_CTL); /* Power up PLL */ + int wt = 0; + while (wt < 100) { if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) dev_warn(edp->dev, "edp pll unlocked.....\n"); + else { + dev_info(edp->dev, "edp pll locked\n"); + break; + } + wt++; + msleep(50); + } /* Enable Serdes FIFO function and Link symbol clock domain module */ val = readl(edp->regs + FUNC_EN_2);