From: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu, 29 Mar 2012 15:32:35 +0000 (-0300)
Subject: drm/i915: add LCPLL control registers
X-Git-Tag: firefly_0821_release~3680^2~2315^2~115^2~15
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=90e8d31c53890064962f1154405e1034be7ec9a1;p=firefly-linux-kernel-4.4.55.git

drm/i915: add LCPLL control registers

Those are used to control the display core clock.

v2: change the enable bit setting, spotted by Rodrigo Vivi.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fe8e2dbef2d..8c44fe0b4fa4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4180,4 +4180,11 @@
 #define  PIPE_CLK_SEL_DISABLED	(0x0<<29)
 #define  PIPE_CLK_SEL_PORT(x)	((x+1)<<29)
 
+/* LCPLL Control */
+#define LCPLL_CTL				0x130040
+#define  LCPLL_PLL_DISABLE		(1<<31)
+#define  LCPLL_PLL_LOCK			(1<<30)
+#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
+#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
+
 #endif /* _I915_REG_H_ */