From: chenxing <chenxing@rock-chips.com>
Date: Thu, 16 May 2013 01:56:55 +0000 (+0800)
Subject: rk3188: chips pll_flag != 0: need to ensure aclk_cpu parent select DO NOT appear... 
X-Git-Tag: firefly_0821_release~7094
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=911b75d46df6861f4b15d75f8e15fa6afb784408;p=firefly-linux-kernel-4.4.55.git

rk3188: chips pll_flag != 0: need to ensure aclk_cpu parent select DO NOT appear high rate
---

diff --git a/arch/arm/mach-rk30/pm.c b/arch/arm/mach-rk30/pm.c
index c09d3a1af0c8..9100a855ff14 100755
--- a/arch/arm/mach-rk30/pm.c
+++ b/arch/arm/mach-rk30/pm.c
@@ -781,11 +781,12 @@ static void rk_pm_soc_pll_suspend(void)
 		clk_sel1 = cru_readl(CRU_CLKSELS_CON(1));
 	
 		cru_writel(PLL_MODE_SLOW(APLL_ID), CRU_MODE_CON);
+		/* To make sure aclk_cpu select gpll before div effect */
+		cru_writel(CPU_SEL_PLL_W_MSK | CPU_SEL_APLL, CRU_CLKSELS_CON(0));
 		cru_writel(CORE_PERIPH_W_MSK | CORE_PERIPH_2
 			   | CORE_CLK_DIV_W_MSK | CORE_CLK_DIV(1)
 			   | CPU_CLK_DIV_W_MSK | CPU_CLK_DIV(1)
 			   | CORE_SEL_PLL_W_MSK | CORE_SEL_APLL
-			   | CPU_SEL_PLL_W_MSK | CPU_SEL_APLL
 			   , CRU_CLKSELS_CON(0));
 		cru_writel(CORE_ACLK_W_MSK | CORE_ACLK_11
 #if !defined(CONFIG_ARCH_RK3188)
@@ -823,7 +824,9 @@ static void rk_pm_soc_pll_resume(void)
 	}
 	//apll
 	cru_writel(0xffff0000 | clk_sel1, CRU_CLKSELS_CON(1));
-	cru_writel(0xffff0000 | clk_sel0, CRU_CLKSELS_CON(0));
+	/* To make sure aclk_cpu select gpll after div effect */
+	cru_writel(0xffdf0000 | clk_sel0, CRU_CLKSELS_CON(0));
+	cru_writel(0x00200000 | clk_sel0, CRU_CLKSELS_CON(0));
 	power_on_pll(APLL_ID);
 	cru_writel((PLL_MODE_MSK(APLL_ID) << 16) | (PLL_MODE_MSK(APLL_ID) & cru_mode_con), CRU_MODE_CON);