From: Xing Zheng <zhengxing@rock-chips.com>
Date: Mon, 9 May 2016 01:29:32 +0000 (+0800)
Subject: clk: rockchip: rk3399: To prevent the dclk_vopx below the FRAC clock
X-Git-Tag: firefly_0821_release~2663
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=92cfd751b4a5ea978caa3fd441b4ccf1f3beea0c;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: rk3399: To prevent the dclk_vopx below the FRAC clock

In most case, we use the VPLL directly for HDMI or DP, and the
the frac dclk will bring the big jitter for dclk. So we don't need
to use the dclk_vopx_frac.

Change-Id: I0d27e5fcb8b4c9a28c0102074c1d6da9426386f4
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 26857790210e..12a8021a99a5 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -159,9 +159,9 @@ PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)	= { "dummy_vpll", "cpll", "gpll",
 						    "xin24m" };
 
 PNAME(mux_dclk_vop0_p)			= { "dclk_vop0_div",
-					    "dclk_vop0_frac" };
+					    "dummy_dclk_vop0_frac" };
 PNAME(mux_dclk_vop1_p)			= { "dclk_vop1_div",
-					    "dclk_vop1_frac" };
+					    "dummy_dclk_vop1_frac" };
 
 PNAME(mux_clk_cif_p)			= { "clk_cifout_src", "xin24m" };