From: Tim Northover Date: Fri, 16 May 2014 09:41:08 +0000 (+0000) Subject: ARM64: give TST aliases priority over ANDS. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=93185d186c42d67ebe28e699ff89ba885f7e062d;p=oota-llvm.git ARM64: give TST aliases priority over ANDS. If an ANDS instruction has Rd == ZR it should be printed as TST since its only effect is on the flags register NZCV. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208959 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index 8ed2c42919b..fe837909ebf 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -726,19 +726,19 @@ def AA_MVNWrs : InstAlias<"mvn $Wd, $Wm$sh", def AA_MVNXrs : InstAlias<"mvn $Xd, $Xm$sh", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh)>; -def : InstAlias<"tst $src1, $src2", - (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>; -def : InstAlias<"tst $src1, $src2", - (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>; +def AA_TSTWri : InstAlias<"tst $src1, $src2", + (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>; +def AA_TSTXri : InstAlias<"tst $src1, $src2", + (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>; -def : InstAlias<"tst $src1, $src2", - (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>; -def : InstAlias<"tst $src1, $src2", - (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>; +def AA_TSTWr: InstAlias<"tst $src1, $src2", + (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>; +def AA_TSTXr: InstAlias<"tst $src1, $src2", + (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>; -def : InstAlias<"tst $src1, $src2, $sh", +def AB_TSTWrs : InstAlias<"tst $src1, $src2$sh", (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh)>; -def : InstAlias<"tst $src1, $src2, $sh", +def AB_TSTXrs : InstAlias<"tst $src1, $src2$sh", (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh)>;