From: Owen Anderson Date: Tue, 26 Aug 2008 18:03:31 +0000 (+0000) Subject: Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=940f83e772ca2007d62faffc83094bd7e8da6401;p=oota-llvm.git Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index b8d939533ba..91ba3ada127 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -221,7 +221,7 @@ public: } /// copyRegToReg - Add a copy between a pair of registers - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index fbceb2fc95a..387929e751a 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -250,9 +250,6 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin, !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) // Unhandled type. Halt "fast" selection and bail. return I; - if (!TLI.isConvertLegal(SrcVT, DstVT)) - // Illegal conversion. Halt "fast" selection and bail. - return I; // Otherwise, insert a register-to-register copy. TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); @@ -264,9 +261,12 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin, // Unhandled operand. Halt "fast" selection and bail. return false; - TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Op0, DstClass, SrcClass); - ValueMap[I] = ResultReg; + bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, + Op0, DstClass, SrcClass); + if (!InsertedCopy) + return I; + ValueMap[I] = ResultReg; break; } else // TODO: Casting a non-integral constant? diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 7fe3b471f27..839ee6a2c56 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -459,14 +459,14 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T return 2; } -void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == ARM::GPRRegisterClass) { @@ -484,7 +484,9 @@ void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB, AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg) .addReg(SrcReg)); else - abort(); + return false; + + return true; } static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB, diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 9fb74c15f3b..815228316a4 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -163,7 +163,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index ec8857fc7f4..b566de45105 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -133,15 +133,15 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 2; } -void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == Alpha::GPRCRegisterClass) { @@ -151,9 +151,11 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } else if (DestRC == Alpha::F8RCRegisterClass) { BuildMI(MBB, MI, get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); + // Attempt to copy register that is not GPR or FPR + return false; } + + return true; } void diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index ccfa429b8a2..9aa5ecd74c7 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -42,7 +42,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 3998b984b21..02490e95c84 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -180,7 +180,7 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { return 0; } -void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, @@ -218,9 +218,11 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg) .addReg(SrcReg); } else { - cerr << "Attempt to copy unknown/unsupported register class!\n"; - abort(); + // Attempt to copy unknown/unsupported register class! + return false; } + + return true; } void diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 9adffde66b9..5f3aaaadf5d 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -46,7 +46,7 @@ namespace llvm { unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index 0fe0a0c37ab..54bcce13c54 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -57,14 +57,14 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, return 1; } -void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode @@ -73,6 +73,8 @@ void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); + + return true; } void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/lib/Target/IA64/IA64InstrInfo.h b/lib/Target/IA64/IA64InstrInfo.h index 61ef0a0a5a0..203f1e851e7 100644 --- a/lib/Target/IA64/IA64InstrInfo.h +++ b/lib/Target/IA64/IA64InstrInfo.h @@ -40,7 +40,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 2d016c67d46..4a919a0a28e 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -118,7 +118,7 @@ insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const BuildMI(MBB, MI, get(Mips::NOP)); } -void MipsInstrInfo:: +bool MipsInstrInfo:: copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, @@ -141,10 +141,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, BuildMI(MBB, I, get(Mips::MTC1A), DestReg).addReg(SrcReg); else if ((SrcRC == Mips::CCRRegisterClass) && (SrcReg == Mips::FCR31)) - return; // This register is used implicitly, no copy needed. + return true; // This register is used implicitly, no copy needed. else if ((DestRC == Mips::CCRRegisterClass) && (DestReg == Mips::FCR31)) - return; // This register is used implicitly, no copy needed. + return true; // This register is used implicitly, no copy needed. else if ((DestRC == Mips::HILORegisterClass) && (SrcRC == Mips::CPURegsRegisterClass)) { unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO; @@ -154,9 +154,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO; BuildMI(MBB, I, get(Opc), DestReg); } else - assert (0 && "DestRC != SrcRC, Can't copy this register"); + // DestRC != SrcRC, Can't copy this register + return false; - return; + return true; } if (DestRC == Mips::CPURegsRegisterClass) @@ -169,7 +170,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, else if (DestRC == Mips::AFGR64RegisterClass) BuildMI(MBB, I, get(Mips::FMOV_D32), DestReg).addReg(SrcReg); else - assert (0 && "Can't copy this register"); + // Can't copy this register + return false; + + return true; } void MipsInstrInfo:: diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index fc7c326d854..7615c715557 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -169,7 +169,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 674b36c5a38..2ec6dcb7d8e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -315,14 +315,14 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 2; } -void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == PPC::GPRCRegisterClass) { @@ -340,9 +340,11 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB, } else if (DestRC == PPC::CRBITRCRegisterClass) { BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg); } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); + // Attempt to copy register that is not GPR or FPR + return false; } + + return true; } bool diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index b7c74fbe768..cb5a0e6c1f6 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -112,7 +112,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 68605a75d47..ab18044d6d4 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -109,14 +109,14 @@ SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, return 1; } -void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); + // Not yet supported! + return false; } if (DestRC == SP::IntRegsRegisterClass) @@ -127,7 +127,10 @@ void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) .addReg(SrcReg); else - assert (0 && "Can't copy this register"); + // Can't copy this register + return false; + + return true; } void SparcInstrInfo:: diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index d19d55f84f6..aadbefd9db0 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -68,7 +68,7 @@ public: MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 6d5f1439f93..4e972592bfa 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1592,7 +1592,7 @@ X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 2; } -void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, +bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, @@ -1626,11 +1626,10 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, } else if (DestRC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64rr; } else { - assert(0 && "Unknown regclass"); - abort(); + return false; } BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg); - return; + return true; } // Moving EFLAGS to / from another register requires a push and a pop. @@ -1639,30 +1638,31 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, if (DestRC == &X86::GR64RegClass) { BuildMI(MBB, MI, get(X86::PUSHFQ)); BuildMI(MBB, MI, get(X86::POP64r), DestReg); - return; + return true; } else if (DestRC == &X86::GR32RegClass) { BuildMI(MBB, MI, get(X86::PUSHFD)); BuildMI(MBB, MI, get(X86::POP32r), DestReg); - return; + return true; } } else if (DestRC == &X86::CCRRegClass) { assert(DestReg == X86::EFLAGS); if (SrcRC == &X86::GR64RegClass) { BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg); BuildMI(MBB, MI, get(X86::POPFQ)); - return; + return true; } else if (SrcRC == &X86::GR32RegClass) { BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg); BuildMI(MBB, MI, get(X86::POPFD)); - return; + return true; } } // Moving from ST(0) turns into FpGET_ST0_32 etc. if (SrcRC == &X86::RSTRegClass) { // Copying from ST(0)/ST(1). - assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) && - "Can only copy from ST(0)/ST(1) right now"); + if (SrcReg != X86::ST0 && SrcReg != X86::ST1) + // Can only copy from ST(0)/ST(1) right now + return false; bool isST0 = SrcReg == X86::ST0; unsigned Opc; if (DestRC == &X86::RFP32RegClass) @@ -1674,13 +1674,15 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; } BuildMI(MBB, MI, get(Opc), DestReg); - return; + return true; } // Moving to ST(0) turns into FpSET_ST0_32 etc. if (DestRC == &X86::RSTRegClass) { // Copying to ST(0). FIXME: handle ST(1) also - assert(DestReg == X86::ST0 && "Can only copy to TOS right now"); + if (DestReg != X86::ST0) + // Can only copy to TOS right now + return false; unsigned Opc; if (SrcRC == &X86::RFP32RegClass) Opc = X86::FpSET_ST0_32; @@ -1691,11 +1693,11 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, Opc = X86::FpSET_ST0_80; } BuildMI(MBB, MI, get(Opc)).addReg(SrcReg); - return; + return true; } - assert(0 && "Not yet supported!"); - abort(); + // Not yet supported! + return false; } static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 0e862e3d13d..2b089f31189 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -311,7 +311,7 @@ public: virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl &Cond) const; - virtual void copyRegToReg(MachineBasicBlock &MBB, + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC,