From: Craig Topper Date: Tue, 26 Jun 2012 04:12:49 +0000 (+0000) Subject: Remove some duplicate instructions that exist only to given different mnemonics for... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=952caee4f66a968f54588cca48215a5008283ea3;p=oota-llvm.git Remove some duplicate instructions that exist only to given different mnemonics for the assembler. Use InstAlias instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 2c12a36f66d..5efb501085e 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1831,12 +1831,10 @@ let Predicates = [HasAVX] in { // Provide other assembly rr and rm forms to address this explicitly. def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; -def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; // XMM only -def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; +def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTPD2DQrr VR128:$dst, VR128:$src)>; def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; @@ -1845,6 +1843,8 @@ def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX; def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L; +def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}", + (VCVTPD2DQYrr VR128:$dst, VR256:$src)>; } def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), @@ -1965,14 +1965,10 @@ def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src), // The assembler can recognize rr 256-bit instructions by seeing a ymm // register, but the same isn't true when using memory operands instead. // Provide other assembly rr and rm forms to address this explicitly. -def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "cvttpd2dq\t{$src, $dst|$dst, $src}", [], - IIC_SSE_CVT_PD_RR>, VEX; // XMM only -def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "cvttpd2dqx\t{$src, $dst|$dst, $src}", [], - IIC_SSE_CVT_PD_RR>, VEX; +def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQrr VR128:$dst, VR128:$src)>; def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvttpd2dqx\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttpd2dq @@ -1986,6 +1982,8 @@ def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L; +def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}", + (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>; let Predicates = [HasAVX] in { def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))), @@ -2083,14 +2081,10 @@ let Predicates = [HasAVX] in { def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2ps\t{$src, $dst|$dst, $src}", [], IIC_SSE_CVT_PD_RR>, VEX; -def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), - "cvtpd2ps\t{$src, $dst|$dst, $src}", [], - IIC_SSE_CVT_PD_RR>, VEX; // XMM only -def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "cvtpd2psx\t{$src, $dst|$dst, $src}", [], - IIC_SSE_CVT_PD_RR>, VEX; +def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}", + (VCVTPD2PSrr VR128:$dst, VR128:$src)>; def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvtpd2psx\t{$src, $dst|$dst, $src}", [], IIC_SSE_CVT_PD_RM>, VEX; @@ -2102,6 +2096,9 @@ def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L; +def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}", + (VCVTPD2PSYrr VR128:$dst, VR256:$src)>; + def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2ps\t{$src, $dst|$dst, $src}", [], IIC_SSE_CVT_PD_RR>; diff --git a/test/MC/X86/x86-32-avx.s b/test/MC/X86/x86-32-avx.s index e13a8712f7d..9a7a50687eb 100644 --- a/test/MC/X86/x86-32-avx.s +++ b/test/MC/X86/x86-32-avx.s @@ -2603,11 +2603,11 @@ // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] vcvttpd2dq %xmm1, %xmm5 -// CHECK: vcvttpd2dq %ymm2, %xmm5 +// CHECK: vcvttpd2dqy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0xe6,0xea] vcvttpd2dq %ymm2, %xmm5 -// CHECK: vcvttpd2dqx %xmm1, %xmm5 +// CHECK: vcvttpd2dq %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] vcvttpd2dqx %xmm1, %xmm5 @@ -2623,11 +2623,11 @@ // CHECK: encoding: [0xc5,0xfd,0xe6,0x08] vcvttpd2dqy (%eax), %xmm1 -// CHECK: vcvtpd2ps %ymm2, %xmm5 +// CHECK: vcvtpd2psy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xfd,0x5a,0xea] vcvtpd2ps %ymm2, %xmm5 -// CHECK: vcvtpd2psx %xmm1, %xmm5 +// CHECK: vcvtpd2ps %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xf9,0x5a,0xe9] vcvtpd2psx %xmm1, %xmm5 @@ -2643,7 +2643,7 @@ // CHECK: encoding: [0xc5,0xfd,0x5a,0x08] vcvtpd2psy (%eax), %xmm1 -// CHECK: vcvtpd2dq %ymm2, %xmm5 +// CHECK: vcvtpd2dqy %ymm2, %xmm5 // CHECK: encoding: [0xc5,0xff,0xe6,0xea] vcvtpd2dq %ymm2, %xmm5 @@ -2655,7 +2655,7 @@ // CHECK: encoding: [0xc5,0xff,0xe6,0x08] vcvtpd2dqy (%eax), %xmm1 -// CHECK: vcvtpd2dqx %xmm1, %xmm5 +// CHECK: vcvtpd2dq %xmm1, %xmm5 // CHECK: encoding: [0xc5,0xfb,0xe6,0xe9] vcvtpd2dqx %xmm1, %xmm5 diff --git a/test/MC/X86/x86_64-avx-encoding.s b/test/MC/X86/x86_64-avx-encoding.s index bd5559a5281..cdc5da42e8c 100644 --- a/test/MC/X86/x86_64-avx-encoding.s +++ b/test/MC/X86/x86_64-avx-encoding.s @@ -3368,11 +3368,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] vcvttpd2dq %xmm11, %xmm10 -// CHECK: vcvttpd2dq %ymm12, %xmm10 +// CHECK: vcvttpd2dqy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xd4] vcvttpd2dq %ymm12, %xmm10 -// CHECK: vcvttpd2dqx %xmm11, %xmm10 +// CHECK: vcvttpd2dq %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] vcvttpd2dqx %xmm11, %xmm10 @@ -3388,11 +3388,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0xe6,0x18] vcvttpd2dqy (%rax), %xmm11 -// CHECK: vcvtpd2ps %ymm12, %xmm10 +// CHECK: vcvtpd2psy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xd4] vcvtpd2ps %ymm12, %xmm10 -// CHECK: vcvtpd2psx %xmm11, %xmm10 +// CHECK: vcvtpd2ps %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xd3] vcvtpd2psx %xmm11, %xmm10 @@ -3408,7 +3408,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7d,0x5a,0x18] vcvtpd2psy (%rax), %xmm11 -// CHECK: vcvtpd2dq %ymm12, %xmm10 +// CHECK: vcvtpd2dqy %ymm12, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xd4] vcvtpd2dq %ymm12, %xmm10 @@ -3420,7 +3420,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x7f,0xe6,0x18] vcvtpd2dqy (%rax), %xmm11 -// CHECK: vcvtpd2dqx %xmm11, %xmm10 +// CHECK: vcvtpd2dq %xmm11, %xmm10 // CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xd3] vcvtpd2dqx %xmm11, %xmm10