From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 14 Feb 2015 03:54:32 +0000 (+0000)
Subject: R600/SI: Really fix size of VReg_1
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=958cf585ce2b78b6ab36e013d5d479753ac2b145;p=oota-llvm.git

R600/SI: Really fix size of VReg_1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229234 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td
index 1a7811f86d6..8b25e9530d4 100644
--- a/lib/Target/R600/SIRegisterInfo.td
+++ b/lib/Target/R600/SIRegisterInfo.td
@@ -209,7 +209,9 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
 
-def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
+def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
+  let Size = 32;
+}
 
 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
   let OperandNamespace = "AMDGPU";