From: luowei <lw@rock-chips.com>
Date: Thu, 19 Dec 2013 10:38:22 +0000 (+0800)
Subject: pinctrl:delete unused code
X-Git-Tag: firefly_0821_release~6434
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=95a82fdadaf2971c36349aaf391d2adb0c040cd6;p=firefly-linux-kernel-4.4.55.git

pinctrl:delete unused code
---

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index f5595c4a6cf0..fff102b4eb50 100755
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1731,7 +1731,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 		generic_handle_irq(virq);
 
 		
-		DBG_PINCTRL("%s:irq=%d\n",__func__, irq);
+		DBG_PINCTRL("%s:irq=%d,%s\n",__func__, irq, bank->name);
 	}
 
 	if (bank->toggle_edge_mode && edge_changed) {
@@ -1824,60 +1824,7 @@ static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	DBG_PINCTRL("%s:type=%d,irq=%d,hwirq=%d,ok\n",__func__,type, d->irq, (int)d->hwirq);
 	return 0;
 }
-#if 0
-static int rockchip_interrupts_register(struct platform_device *pdev,
-						struct rockchip_pinctrl *info)
-{
-	struct rockchip_pin_ctrl *ctrl = info->ctrl;
-	struct rockchip_pin_bank *bank = ctrl->pin_banks;
-	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
-	struct irq_chip_generic *gc;
-	int ret;
-	int i;
-
-	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
-		if (!bank->valid) {
-			dev_warn(&pdev->dev, "bank %s is not valid\n",
-				 bank->name);
-			continue;
-		}
 
-		bank->domain = irq_domain_add_linear(bank->of_node, 32,
-						&irq_generic_chip_ops, NULL);
-		if (!bank->domain) {
-			dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
-				 bank->name);
-			continue;
-		}
-
-		ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
-					 "rockchip_gpio_irq", handle_level_irq,
-					 clr, 0, IRQ_GC_INIT_MASK_CACHE);
-		if (ret) {
-			dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
-				bank->name);
-			irq_domain_remove(bank->domain);
-			continue;
-		}
-
-		gc = irq_get_domain_generic_chip(bank->domain, 0);
-		gc->reg_base = bank->reg_base;
-		gc->private = bank;
-		gc->chip_types[0].regs.mask = GPIO_INTEN;
-		gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
-		gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
-		gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
-		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
-		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
-		gc->chip_types[0].chip.irq_set_type = rockchip_gpio_irq_set_type;
-
-		irq_set_handler_data(bank->irq, bank);
-		irq_set_chained_handler(bank->irq, rockchip_irq_demux);
-	}
-
-	return 0;
-}
-#else
 
 static inline void rockchip_gpio_bit_op(void __iomem *reg_base, unsigned int offset, u32 bit, unsigned char flag)
 {
@@ -1901,25 +1848,7 @@ static inline unsigned offset_to_bit(unsigned offset)
 {
 	return 1u << offset;
 }
-#if 0
-static void GPIOSetPinLevel(void __iomem *reg_base, unsigned int bit, eGPIOPinLevel_t level)
-{
-	rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, 1);
-	rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DR, bit, level);
-}
-
-static int GPIOGetPinLevel(void __iomem *reg_base, unsigned int bit)
-{
-	return ((__raw_readl(reg_base + GPIO_EXT_PORT) & bit) != 0);
-}
 
-static void GPIOSetPinDirection(void __iomem *reg_base, unsigned int bit, eGPIOPinDirection_t direction)
-{
-	rockchip_gpio_bit_op(reg_base, GPIO_SWPORT_DDR, bit, direction);
-	/* Enable debounce may halt cpu on wfi, disable it by default */
-	//rockchip_gpio_bit_op(reg_base, GPIO_DEBOUNCE, bit, 1);
-}
-#endif
 static void GPIOEnableIntr(void __iomem *reg_base, unsigned int bit)
 {
 	rockchip_gpio_bit_op(reg_base, GPIO_INTEN, bit, 1);
@@ -1934,67 +1863,7 @@ static void GPIOAckIntr(void __iomem *reg_base, unsigned int bit)
 {
 	rockchip_gpio_bit_op(reg_base, GPIO_PORTS_EOI, bit, 1);
 }
-#if 0
-static void GPIOSetIntrType(void __iomem *reg_base, unsigned int bit, eGPIOIntType_t type)
-{
-	switch (type) {
-	case GPIOLevelLow:
-		rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
-		rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
-		break;
-	case GPIOLevelHigh:
-		rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 0);
-		rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
-		break;
-	case GPIOEdgelFalling:
-		rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
-		rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 0);
-		break;
-	case GPIOEdgelRising:
-		rockchip_gpio_bit_op(reg_base, GPIO_INTTYPE_LEVEL, bit, 1);
-		rockchip_gpio_bit_op(reg_base, GPIO_INT_POLARITY, bit, 1);
-		break;
-	}
-}
-
-static int rockchip_gpio_irq_set_type(struct irq_data *d, unsigned int type)
-{
-	struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);
-	u32 bit = gpio_to_bit(irq_to_gpio(d->irq));
-	eGPIOIntType_t int_type;
-	unsigned long flags;
 
-	switch (type) {
-	case IRQ_TYPE_EDGE_RISING:
-		int_type = GPIOEdgelRising;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		int_type = GPIOEdgelFalling;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		int_type = GPIOLevelHigh;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		int_type = GPIOLevelLow;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	spin_lock_irqsave(&bank->slock, flags);
-	//ÉèÖÃΪÖжÏ֮ǰ£¬±ØÐëÏÈÉèÖÃΪÊäÈë״̬
-	GPIOSetPinDirection(bank->reg_base, bit, 0);
-	GPIOSetIntrType(bank->reg_base, bit, int_type);
-	spin_unlock_irqrestore(&bank->slock, flags);
-
-	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-		__irq_set_handler_locked(d->irq, handle_level_irq);
-	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-		__irq_set_handler_locked(d->irq, handle_edge_irq);
-
-	return 0;
-}
-#endif
 static int rockchip_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
 	struct rockchip_pin_bank *bank = irq_data_get_irq_chip_data(d);	
@@ -2138,7 +2007,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
 }
 
 
-#endif
 static int rockchip_gpiolib_register(struct platform_device *pdev,
 						struct rockchip_pinctrl *info)
 {
@@ -2295,13 +2163,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
 
 	return ctrl;
 }
-#if 0
-static irqreturn_t pinctrl_interrupt_test(int irq, void *dev_id)
-{
-	printk("%s:line=%d\n",__func__, __LINE__);
-	return IRQ_HANDLED;
-}
-#endif
+
 static int rockchip_pinctrl_probe(struct platform_device *pdev)
 {
 	struct rockchip_pinctrl *info;
@@ -2353,19 +2215,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, info);
-#if 0
-	int i = 0;
-	for(i=1; i<32*4; i++)
-	{
-		if(i>23 && i<32+16)
-		continue;
-		gpio_request(i, NULL);	
-		gpio_direction_input(i);
-		
-		ret = request_irq(gpio_to_irq(i), pinctrl_interrupt_test, IRQ_TYPE_EDGE_RISING, "test", info);
-		disable_irq(gpio_to_irq(i));
-	}
-#endif
+
 	printk("%s:init ok\n",__func__);
 	return 0;
 }
diff --git a/include/dt-bindings/pinctrl/rockchip-rk3188.h b/include/dt-bindings/pinctrl/rockchip-rk3188.h
index 701e4ba8d3aa..d0e4ba5b7849 100755
--- a/include/dt-bindings/pinctrl/rockchip-rk3188.h
+++ b/include/dt-bindings/pinctrl/rockchip-rk3188.h
@@ -489,8 +489,8 @@
 #define VALUE_PULL_DEFAULT	3
 
 #define VALUE_VOL_DEFAULT	0
-#define VALUE_VOL_33V		0
-#define VALUE_VOL_18V		1
+#define VALUE_VOL_3V3		0
+#define VALUE_VOL_1V8		1
 
 #define VALUE_DRV_DEFAULT	0
 #define VALUE_DRV_2MA		0
@@ -539,190 +539,37 @@
 //#define rk30_mux_api_set(name, mode) iomux_set(mode)
 //#define rk30_iomux_init() iomux_init()
 
-#define NUM_GROUP			32
-#define PIN_BASE			0
-
-#define	RK30_PIN0_PA0		(0*NUM_GROUP + PIN_BASE + 0)
-#define	RK30_PIN0_PA1		(0*NUM_GROUP + PIN_BASE + 1)
-#define	RK30_PIN0_PA2		(0*NUM_GROUP + PIN_BASE + 2)
-#define	RK30_PIN0_PA3		(0*NUM_GROUP + PIN_BASE + 3)
-#define	RK30_PIN0_PA4		(0*NUM_GROUP + PIN_BASE + 4)
-#define	RK30_PIN0_PA5		(0*NUM_GROUP + PIN_BASE + 5)
-#define	RK30_PIN0_PA6		(0*NUM_GROUP + PIN_BASE + 6)
-#define	RK30_PIN0_PA7		(0*NUM_GROUP + PIN_BASE + 7)
-#define	RK30_PIN0_PB0		(0*NUM_GROUP + PIN_BASE + 8)
-#define	RK30_PIN0_PB1		(0*NUM_GROUP + PIN_BASE + 9)
-#define	RK30_PIN0_PB2		(0*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN0_PB3		(0*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN0_PB4		(0*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN0_PB5		(0*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN0_PB6		(0*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN0_PB7		(0*NUM_GROUP + PIN_BASE + 15)
-#define	RK30_PIN0_PC0		(0*NUM_GROUP + PIN_BASE + 16)
-#define	RK30_PIN0_PC1		(0*NUM_GROUP + PIN_BASE + 17)
-#define	RK30_PIN0_PC2		(0*NUM_GROUP + PIN_BASE + 18)
-#define	RK30_PIN0_PC3		(0*NUM_GROUP + PIN_BASE + 19)
-#define	RK30_PIN0_PC4		(0*NUM_GROUP + PIN_BASE + 20)
-#define	RK30_PIN0_PC5		(0*NUM_GROUP + PIN_BASE + 21)
-#define	RK30_PIN0_PC6		(0*NUM_GROUP + PIN_BASE + 22)
-#define	RK30_PIN0_PC7		(0*NUM_GROUP + PIN_BASE + 23)
-#define	RK30_PIN0_PD0		(0*NUM_GROUP + PIN_BASE + 24)
-#define	RK30_PIN0_PD1		(0*NUM_GROUP + PIN_BASE + 25)
-#define	RK30_PIN0_PD2		(0*NUM_GROUP + PIN_BASE + 26)
-#define	RK30_PIN0_PD3		(0*NUM_GROUP + PIN_BASE + 27)
-#define	RK30_PIN0_PD4		(0*NUM_GROUP + PIN_BASE + 28)
-#define	RK30_PIN0_PD5		(0*NUM_GROUP + PIN_BASE + 29)
-#define	RK30_PIN0_PD6		(0*NUM_GROUP + PIN_BASE + 30)
-#define	RK30_PIN0_PD7		(0*NUM_GROUP + PIN_BASE + 31)
-
-#define	RK30_PIN1_PA0		(1*NUM_GROUP + PIN_BASE + 0) 
-#define	RK30_PIN1_PA1		(1*NUM_GROUP + PIN_BASE + 1) 
-#define	RK30_PIN1_PA2		(1*NUM_GROUP + PIN_BASE + 2) 
-#define	RK30_PIN1_PA3		(1*NUM_GROUP + PIN_BASE + 3) 
-#define	RK30_PIN1_PA4		(1*NUM_GROUP + PIN_BASE + 4) 
-#define	RK30_PIN1_PA5		(1*NUM_GROUP + PIN_BASE + 5) 
-#define	RK30_PIN1_PA6		(1*NUM_GROUP + PIN_BASE + 6) 
-#define	RK30_PIN1_PA7		(1*NUM_GROUP + PIN_BASE + 7) 
-#define	RK30_PIN1_PB0		(1*NUM_GROUP + PIN_BASE + 8) 
-#define	RK30_PIN1_PB1		(1*NUM_GROUP + PIN_BASE + 9) 
-#define	RK30_PIN1_PB2		(1*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN1_PB3		(1*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN1_PB4		(1*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN1_PB5		(1*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN1_PB6		(1*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN1_PB7		(1*NUM_GROUP + PIN_BASE + 15)
-#define	RK30_PIN1_PC0		(1*NUM_GROUP + PIN_BASE + 16)
-#define	RK30_PIN1_PC1		(1*NUM_GROUP + PIN_BASE + 17)
-#define	RK30_PIN1_PC2		(1*NUM_GROUP + PIN_BASE + 18)
-#define	RK30_PIN1_PC3		(1*NUM_GROUP + PIN_BASE + 19)
-#define	RK30_PIN1_PC4		(1*NUM_GROUP + PIN_BASE + 20)
-#define	RK30_PIN1_PC5		(1*NUM_GROUP + PIN_BASE + 21)
-#define	RK30_PIN1_PC6		(1*NUM_GROUP + PIN_BASE + 22)
-#define	RK30_PIN1_PC7		(1*NUM_GROUP + PIN_BASE + 23)
-#define	RK30_PIN1_PD0		(1*NUM_GROUP + PIN_BASE + 24)
-#define	RK30_PIN1_PD1		(1*NUM_GROUP + PIN_BASE + 25)
-#define	RK30_PIN1_PD2		(1*NUM_GROUP + PIN_BASE + 26)
-#define	RK30_PIN1_PD3		(1*NUM_GROUP + PIN_BASE + 27)
-#define	RK30_PIN1_PD4		(1*NUM_GROUP + PIN_BASE + 28)
-#define	RK30_PIN1_PD5		(1*NUM_GROUP + PIN_BASE + 29)
-#define	RK30_PIN1_PD6		(1*NUM_GROUP + PIN_BASE + 30)
-#define	RK30_PIN1_PD7		(1*NUM_GROUP + PIN_BASE + 31)
-
-#define	RK30_PIN2_PA0		(2*NUM_GROUP + PIN_BASE + 0)
-#define	RK30_PIN2_PA1		(2*NUM_GROUP + PIN_BASE + 1)
-#define	RK30_PIN2_PA2		(2*NUM_GROUP + PIN_BASE + 2)
-#define	RK30_PIN2_PA3		(2*NUM_GROUP + PIN_BASE + 3)
-#define	RK30_PIN2_PA4		(2*NUM_GROUP + PIN_BASE + 4)
-#define	RK30_PIN2_PA5		(2*NUM_GROUP + PIN_BASE + 5)
-#define	RK30_PIN2_PA6		(2*NUM_GROUP + PIN_BASE + 6)
-#define	RK30_PIN2_PA7		(2*NUM_GROUP + PIN_BASE + 7)
-#define	RK30_PIN2_PB0		(2*NUM_GROUP + PIN_BASE + 8)
-#define	RK30_PIN2_PB1		(2*NUM_GROUP + PIN_BASE + 9)
-#define	RK30_PIN2_PB2		(2*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN2_PB3		(2*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN2_PB4		(2*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN2_PB5		(2*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN2_PB6		(2*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN2_PB7		(2*NUM_GROUP + PIN_BASE + 15)
-#define	RK30_PIN2_PC0		(2*NUM_GROUP + PIN_BASE + 16)
-#define	RK30_PIN2_PC1		(2*NUM_GROUP + PIN_BASE + 17)
-#define	RK30_PIN2_PC2		(2*NUM_GROUP + PIN_BASE + 18)
-#define	RK30_PIN2_PC3		(2*NUM_GROUP + PIN_BASE + 19)
-#define	RK30_PIN2_PC4		(2*NUM_GROUP + PIN_BASE + 20)
-#define	RK30_PIN2_PC5		(2*NUM_GROUP + PIN_BASE + 21)
-#define	RK30_PIN2_PC6		(2*NUM_GROUP + PIN_BASE + 22)
-#define	RK30_PIN2_PC7		(2*NUM_GROUP + PIN_BASE + 23)
-#define	RK30_PIN2_PD0		(2*NUM_GROUP + PIN_BASE + 24)
-#define	RK30_PIN2_PD1		(2*NUM_GROUP + PIN_BASE + 25)
-#define	RK30_PIN2_PD2		(2*NUM_GROUP + PIN_BASE + 26)
-#define	RK30_PIN2_PD3		(2*NUM_GROUP + PIN_BASE + 27)
-#define	RK30_PIN2_PD4		(2*NUM_GROUP + PIN_BASE + 28)
-#define	RK30_PIN2_PD5		(2*NUM_GROUP + PIN_BASE + 29)
-#define	RK30_PIN2_PD6		(2*NUM_GROUP + PIN_BASE + 30)
-#define	RK30_PIN2_PD7		(2*NUM_GROUP + PIN_BASE + 31)
-
-#define	RK30_PIN3_PA0		(3*NUM_GROUP + PIN_BASE + 0) 
-#define	RK30_PIN3_PA1		(3*NUM_GROUP + PIN_BASE + 1) 
-#define	RK30_PIN3_PA2		(3*NUM_GROUP + PIN_BASE + 2) 
-#define	RK30_PIN3_PA3		(3*NUM_GROUP + PIN_BASE + 3) 
-#define	RK30_PIN3_PA4		(3*NUM_GROUP + PIN_BASE + 4) 
-#define	RK30_PIN3_PA5		(3*NUM_GROUP + PIN_BASE + 5) 
-#define	RK30_PIN3_PA6		(3*NUM_GROUP + PIN_BASE + 6) 
-#define	RK30_PIN3_PA7		(3*NUM_GROUP + PIN_BASE + 7) 
-#define	RK30_PIN3_PB0		(3*NUM_GROUP + PIN_BASE + 8) 
-#define	RK30_PIN3_PB1		(3*NUM_GROUP + PIN_BASE + 9) 
-#define	RK30_PIN3_PB2		(3*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN3_PB3		(3*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN3_PB4		(3*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN3_PB5		(3*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN3_PB6		(3*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN3_PB7		(3*NUM_GROUP + PIN_BASE + 15)
-#define	RK30_PIN3_PC0		(3*NUM_GROUP + PIN_BASE + 16)
-#define	RK30_PIN3_PC1		(3*NUM_GROUP + PIN_BASE + 17)
-#define	RK30_PIN3_PC2		(3*NUM_GROUP + PIN_BASE + 18)
-#define	RK30_PIN3_PC3		(3*NUM_GROUP + PIN_BASE + 19)
-#define	RK30_PIN3_PC4		(3*NUM_GROUP + PIN_BASE + 20)
-#define	RK30_PIN3_PC5		(3*NUM_GROUP + PIN_BASE + 21)
-#define	RK30_PIN3_PC6		(3*NUM_GROUP + PIN_BASE + 22)
-#define	RK30_PIN3_PC7		(3*NUM_GROUP + PIN_BASE + 23)
-#define	RK30_PIN3_PD0		(3*NUM_GROUP + PIN_BASE + 24)
-#define	RK30_PIN3_PD1		(3*NUM_GROUP + PIN_BASE + 25)
-#define	RK30_PIN3_PD2		(3*NUM_GROUP + PIN_BASE + 26)
-#define	RK30_PIN3_PD3		(3*NUM_GROUP + PIN_BASE + 27)
-#define	RK30_PIN3_PD4		(3*NUM_GROUP + PIN_BASE + 28)
-#define	RK30_PIN3_PD5		(3*NUM_GROUP + PIN_BASE + 29)
-#define	RK30_PIN3_PD6		(3*NUM_GROUP + PIN_BASE + 30)
-#define	RK30_PIN3_PD7		(3*NUM_GROUP + PIN_BASE + 31)
-
-#define	RK30_PIN4_PA0		(4*NUM_GROUP + PIN_BASE + 0) 
-#define	RK30_PIN4_PA1		(4*NUM_GROUP + PIN_BASE + 1) 
-#define	RK30_PIN4_PA2		(4*NUM_GROUP + PIN_BASE + 2) 
-#define	RK30_PIN4_PA3		(4*NUM_GROUP + PIN_BASE + 3) 
-#define	RK30_PIN4_PA4		(4*NUM_GROUP + PIN_BASE + 4) 
-#define	RK30_PIN4_PA5		(4*NUM_GROUP + PIN_BASE + 5) 
-#define	RK30_PIN4_PA6		(4*NUM_GROUP + PIN_BASE + 6) 
-#define	RK30_PIN4_PA7		(4*NUM_GROUP + PIN_BASE + 7) 
-#define	RK30_PIN4_PB0		(4*NUM_GROUP + PIN_BASE + 8) 
-#define	RK30_PIN4_PB1		(4*NUM_GROUP + PIN_BASE + 9) 
-#define	RK30_PIN4_PB2		(4*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN4_PB3		(4*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN4_PB4		(4*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN4_PB5		(4*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN4_PB6		(4*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN4_PB7		(4*NUM_GROUP + PIN_BASE + 15)
-#define	RK30_PIN4_PC0		(4*NUM_GROUP + PIN_BASE + 16)
-#define	RK30_PIN4_PC1		(4*NUM_GROUP + PIN_BASE + 17)
-#define	RK30_PIN4_PC2		(4*NUM_GROUP + PIN_BASE + 18)
-#define	RK30_PIN4_PC3		(4*NUM_GROUP + PIN_BASE + 19)
-#define	RK30_PIN4_PC4		(4*NUM_GROUP + PIN_BASE + 20)
-#define	RK30_PIN4_PC5		(4*NUM_GROUP + PIN_BASE + 21)
-#define	RK30_PIN4_PC6		(4*NUM_GROUP + PIN_BASE + 22)
-#define	RK30_PIN4_PC7		(4*NUM_GROUP + PIN_BASE + 23)
-#define	RK30_PIN4_PD0		(4*NUM_GROUP + PIN_BASE + 24)
-#define	RK30_PIN4_PD1		(4*NUM_GROUP + PIN_BASE + 25)
-#define	RK30_PIN4_PD2		(4*NUM_GROUP + PIN_BASE + 26)
-#define	RK30_PIN4_PD3		(4*NUM_GROUP + PIN_BASE + 27)
-#define	RK30_PIN4_PD4		(4*NUM_GROUP + PIN_BASE + 28)
-#define	RK30_PIN4_PD5		(4*NUM_GROUP + PIN_BASE + 29)
-#define	RK30_PIN4_PD6		(4*NUM_GROUP + PIN_BASE + 30)
-#define	RK30_PIN4_PD7		(4*NUM_GROUP + PIN_BASE + 31)
-
-#define	RK30_PIN6_PA0		(6*NUM_GROUP + PIN_BASE + 0)
-#define	RK30_PIN6_PA1		(6*NUM_GROUP + PIN_BASE + 1)
-#define	RK30_PIN6_PA2		(6*NUM_GROUP + PIN_BASE + 2)
-#define	RK30_PIN6_PA3		(6*NUM_GROUP + PIN_BASE + 3)
-#define	RK30_PIN6_PA4		(6*NUM_GROUP + PIN_BASE + 4)
-#define	RK30_PIN6_PA5		(6*NUM_GROUP + PIN_BASE + 5)
-#define	RK30_PIN6_PA6		(6*NUM_GROUP + PIN_BASE + 6)
-#define	RK30_PIN6_PA7		(6*NUM_GROUP + PIN_BASE + 7)
-#define	RK30_PIN6_PB0		(6*NUM_GROUP + PIN_BASE + 8)
-#define	RK30_PIN6_PB1		(6*NUM_GROUP + PIN_BASE + 9)
-#define	RK30_PIN6_PB2		(6*NUM_GROUP + PIN_BASE + 10)
-#define	RK30_PIN6_PB3		(6*NUM_GROUP + PIN_BASE + 11)
-#define	RK30_PIN6_PB4		(6*NUM_GROUP + PIN_BASE + 12)
-#define	RK30_PIN6_PB5		(6*NUM_GROUP + PIN_BASE + 13)
-#define	RK30_PIN6_PB6		(6*NUM_GROUP + PIN_BASE + 14)
-#define	RK30_PIN6_PB7		(6*NUM_GROUP + PIN_BASE + 15)
-
+#define	RK30_PIN_PA0		( 0)
+#define	RK30_PIN_PA1		( 1)
+#define	RK30_PIN_PA2		( 2)
+#define	RK30_PIN_PA3		( 3)
+#define	RK30_PIN_PA4		( 4)
+#define	RK30_PIN_PA5		( 5)
+#define	RK30_PIN_PA6		( 6)
+#define	RK30_PIN_PA7		( 7)
+#define	RK30_PIN_PB0		( 8)
+#define	RK30_PIN_PB1		( 9)
+#define	RK30_PIN_PB2		( 10)
+#define	RK30_PIN_PB3		( 11)
+#define	RK30_PIN_PB4		( 12)
+#define	RK30_PIN_PB5		( 13)
+#define	RK30_PIN_PB6		( 14)
+#define	RK30_PIN_PB7		( 15)
+#define	RK30_PIN_PC0		( 16)
+#define	RK30_PIN_PC1		( 17)
+#define	RK30_PIN_PC2		( 18)
+#define	RK30_PIN_PC3		( 19)
+#define	RK30_PIN_PC4		( 20)
+#define	RK30_PIN_PC5		( 21)
+#define	RK30_PIN_PC6		( 22)
+#define	RK30_PIN_PC7		( 23)
+#define	RK30_PIN_PD0		( 24)
+#define	RK30_PIN_PD1		( 25)
+#define	RK30_PIN_PD2		( 26)
+#define	RK30_PIN_PD3		( 27)
+#define	RK30_PIN_PD4		( 28)
+#define	RK30_PIN_PD5		( 29)
+#define	RK30_PIN_PD6		( 30)
+#define	RK30_PIN_PD7		( 31)
 
 #endif