From: Stephen Warren <swarren@nvidia.com>
Date: Wed, 5 Jan 2011 00:47:55 +0000 (-0700)
Subject: ARM: tegra: pll_a clock fixes
X-Git-Tag: firefly_0821_release~9833^2~69^2
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=962feda6df4542dfae908df64504c8e8046db1d4;p=firefly-linux-kernel-4.4.55.git

ARM: tegra: pll_a clock fixes

Increase the max_frequency entries for clocks that can be driven from pll_a
to match the fastest pll_a table entry.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
---

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 692bb845d588..d3e17c1621f7 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1475,7 +1475,7 @@ static struct clk tegra_pll_a = {
 	.ops       = &tegra_pll_ops,
 	.reg       = 0xb0,
 	.parent    = &tegra_pll_p_out1,
-	.max_rate  = 56448000,
+	.max_rate  = 73728000,
 	.u.pll = {
 		.input_min = 2000000,
 		.input_max = 31000000,
@@ -1495,7 +1495,7 @@ static struct clk tegra_pll_a_out0 = {
 	.parent    = &tegra_pll_a,
 	.reg       = 0xb4,
 	.reg_shift = 0,
-	.max_rate  = 56448000,
+	.max_rate  = 73728000,
 };
 
 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
@@ -1694,7 +1694,7 @@ static struct clk tegra_clk_audio = {
 	.name      = "audio",
 	.inputs    = mux_audio_sync_clk,
 	.reg       = 0x38,
-	.max_rate  = 24000000,
+	.max_rate  = 73728000,
 	.ops       = &tegra_audio_sync_clk_ops
 };