From: Akira Hatanaka <ahatanaka@mips.com>
Date: Fri, 26 Jul 2013 20:58:55 +0000 (+0000)
Subject: [mips] Implement llvm.trap intrinsic.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9758562aa706a5a20a9d833074e733ed544db776;p=oota-llvm.git

[mips] Implement llvm.trap intrinsic.

Patch by Sasa Stankovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 8bf4249af1e..b6b4c2ab02d 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -385,6 +385,8 @@ MipsTargetLowering(MipsTargetMachine &TM)
     setTruncStoreAction(MVT::i64, MVT::i32, Custom);
   }
 
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+
   setTargetDAGCombine(ISD::SDIVREM);
   setTargetDAGCombine(ISD::UDIVREM);
   setTargetDAGCombine(ISD::SELECT);
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 5e2c68744a5..83afcce98a9 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -826,6 +826,11 @@ class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
 class MFC3OP<dag outs, dag ins, string asmstr> :
   InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
 
+let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
+def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
+   let Inst = 0x0000000d;
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo instructions
 //===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/Mips/trap.ll b/test/CodeGen/Mips/trap.ll
new file mode 100644
index 00000000000..beb4b894632
--- /dev/null
+++ b/test/CodeGen/Mips/trap.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
+
+declare void @llvm.trap()
+
+define void @f1() {
+entry:
+  call void @llvm.trap()
+  unreachable
+
+; CHECK:        break
+}