From: 张晴 <zhangqing@rock-chips.com>
Date: Fri, 1 Aug 2014 02:48:01 +0000 (+0800)
Subject: rk312x:clk:support clk pd,set cpll for any freq
X-Git-Tag: firefly_0821_release~4916^2~90
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=97a6355e4aaf2cbb3c2a61b66b1651df6595c634;p=firefly-linux-kernel-4.4.55.git

rk312x:clk:support clk pd,set cpll for any freq
---

diff --git a/arch/arm/boot/dts/rk312x-clocks.dtsi b/arch/arm/boot/dts/rk312x-clocks.dtsi
index 79ddde0039d0..d1b1ab073ec0 100755
--- a/arch/arm/boot/dts/rk312x-clocks.dtsi
+++ b/arch/arm/boot/dts/rk312x-clocks.dtsi
@@ -157,6 +157,97 @@
 
 		};
 
+		pd_cons {
+			compatible = "rockchip,rk-pd-cons";
+
+			pd_gpu: pd_gpu {
+				compatible = "rockchip,rk-pd-clock";
+				clock-output-names = "pd_gpu";
+				rockchip,pd-id = <CLK_PD_GPU>;
+				#clock-cells = <0>;
+			};
+
+			pd_video: pd_video {
+				compatible = "rockchip,rk-pd-clock";
+				clock-output-names = "pd_video";
+				rockchip,pd-id = <CLK_PD_VIDEO>;
+				#clock-cells = <0>;
+			};
+
+			pd_vio: pd_vio {
+				compatible = "rockchip,rk-pd-clock";
+				clock-output-names = "pd_vio";
+				rockchip,pd-id = <CLK_PD_VIO>;
+				#clock-cells = <0>;
+			};
+
+			pd_vop0: pd_vop0 {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_vop0";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_vop1: pd_vop1 {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_vop1";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_vip: pd_vip {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_vip";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_iep: pd_iep {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_iep";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_rga: pd_rga {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_rga";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_ebc: pd_ebc {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_ebc";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_mipidsi: pd_mipidsi {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_mipidsi";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+			pd_hdmi: pd_hdmi {
+				compatible = "rockchip,rk-pd-clock";
+				clocks = <&pd_vio>;
+				clock-output-names = "pd_hdmi";
+				rockchip,pd-id = <CLK_PD_VIRT>;
+				#clock-cells = <0>;
+			};
+
+		};
+
+
 		clock_regs {
 			compatible = "rockchip,rk-clock-regs";
 			#address-cells = <1>;
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index a4fe2c1f645d..c092f831bfcf 100755
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1722,15 +1722,14 @@ static const struct clk_ops clk_pll_ops_3036plus_auto = {
 static long clk_cpll_round_rate_312xplus(struct clk_hw *hw, unsigned long rate,
 		unsigned long *prate)
 {
-	struct clk *parent = __clk_get_parent(hw->clk);
+	unsigned long best;
 
-	if (parent && (rate == __clk_get_rate(parent))) {
-		clk_debug("pll %s round rate=%lu equal to parent rate\n",
-				__clk_get_name(hw->clk), rate);
-		return rate;
+	for (best = rate; best > 0; best--) {
+		if (!pll_clk_get_best_set(*prate, best, NULL, NULL, NULL))
+			return best;
 	}
 
-	return (pll_com_get_best_set(rate, rk312xplus_pll_com_table)->rate);
+	return 0;
 }
 
 static int clk_cpll_set_rate_312xplus(struct clk_hw *hw, unsigned long rate,