From: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Date: Tue, 5 May 2015 19:34:10 +0000 (+0000)
Subject: [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=97dbeaa8d596f1b6963211f8e5683b4735d66ff8;p=oota-llvm.git

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

This patch makes ReplaceExtractVectorEltOfLoadWithNarrowedLoad convert
the element number from getVectorIdxTy() to PtrTy before doing pointer
arithmetic on it.  This is needed on z, where element numbers are i32
but pointers are i64.

Original patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236530 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4669d6c2f18..bf42aabeab2 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11416,9 +11416,10 @@ SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
     Offset = DAG.getConstant(PtrOff, DL, PtrType);
     MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
   } else {
+    Offset = DAG.getZExtOrTrunc(EltNo, DL, PtrType);
     Offset = DAG.getNode(
-        ISD::MUL, DL, EltNo.getValueType(), EltNo,
-        DAG.getConstant(VecEltVT.getStoreSize(), DL, EltNo.getValueType()));
+        ISD::MUL, DL, PtrType, Offset,
+        DAG.getConstant(VecEltVT.getStoreSize(), DL, PtrType));
     MPI = OriginalLoad->getPointerInfo();
   }
   NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, NewPtr, Offset);
diff --git a/test/CodeGen/SystemZ/vec-extract-02.ll b/test/CodeGen/SystemZ/vec-extract-02.ll
new file mode 100644
index 00000000000..c91e852fcf4
--- /dev/null
+++ b/test/CodeGen/SystemZ/vec-extract-02.ll
@@ -0,0 +1,15 @@
+; Verify ReplaceExtractVectorEltOfLoadWithNarrowedLoad fixes
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
+
+; Test a case where a vector extraction can be simplified to a scalar load.
+; The index must be extended from i32 to i64.
+define i32 @f1(<4 x i32> *%ptr, i32 %index) {
+; CHECK-LABEL: f1:
+; CHECK: risbg {{%r[0-5]}}, %r3, 30, 189, 2
+; CHECK: l %r2,
+; CHECK: br %r14
+  %vec = load <4 x i32>, <4 x i32> *%ptr
+  %res = extractelement <4 x i32> %vec, i32 %index
+  ret i32 %res
+}