From: chenxing <chenxing@rock-chips.com>
Date: Tue, 9 Jul 2013 03:08:40 +0000 (+0800)
Subject: rk3188: Priority setting i2s under cpll to fix i2s frac div do not effect, let axi_cp... 
X-Git-Tag: firefly_0821_release~6924
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=981f1d9f9634e84fbb3f55e8547aba44cdf18ea9;p=firefly-linux-kernel-4.4.55.git

rk3188: Priority setting i2s under cpll to fix i2s frac div do not effect, let axi_cpu's pll different with i2s's
---

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 4d0f734e608b..10ddea3c72ea 100755
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -3413,10 +3413,14 @@ void rk30_clock_common_i2s_init(void)
 		i2s_rate = 49152000;
 	}
 
-	if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
-		clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
-	} else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
+	/*
+	 * Priority setting i2s under cpll to fix i2s frac div do not effect, let
+	 * axi_cpu's pll different with i2s's
+	 * */
+	if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
 		clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
+	} else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
+		clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
 	} else {
 		if(general_pll_clk.rate > codec_pll_clk.rate)
 			clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);