From: chenxing <chenxing@rock-chips.com>
Date: Fri, 21 Jun 2013 09:14:21 +0000 (+0800)
Subject: rk3066: support set_rate_even div = 1
X-Git-Tag: firefly_0821_release~6965^2~34
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=98db31bfb5fd5115eda32a1684a80f21d9579bc8;p=firefly-linux-kernel-4.4.55.git

rk3066: support set_rate_even div = 1
---

diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c
index 927d271d15b4..1394e1ddbe78 100644
--- a/arch/arm/mach-rk30/clock_data.c
+++ b/arch/arm/mach-rk30/clock_data.c
@@ -298,9 +298,11 @@ static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
 //for div 1 2 4 2*n
 static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
 {
-	u32 div;
-	for (div = 2; div < clk->div_max; div += 2) {
-		u32 new_rate = clk->parent->rate / div;
+	u32 div = 0, new_rate = 0;
+	for (div = 1; div < clk->div_max; div++) {
+		if (div >= 3 && div % 2 != 0)
+			continue;
+		new_rate = clk->parent->rate / div;
 		if (new_rate <= rate) {
 			set_cru_bits_w_msk(div - 1, clk->div_mask, clk->div_shift, clk->clksel_con);
 			clk->rate = new_rate;