From: Todd Poynor <toddpoynor@google.com>
Date: Wed, 16 Feb 2011 20:25:36 +0000 (-0800)
Subject: ARM: tegra: Enable PL310 dynamic clock gating
X-Git-Tag: firefly_0821_release~9833^2~30^2~8
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=996d8ccfe7ee48dabe8f46358159985e0a410c08;p=firefly-linux-kernel-4.4.55.git

ARM: tegra: Enable PL310 dynamic clock gating

The cache controller will stop its clock when idle after several
clock cycles.

Change-Id: Ifc9997d4e7fd4f1e3c6129bac2fd42f8995a069e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
---

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5283a17f3d2b..b1275e7207f8 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -89,6 +89,7 @@ void __init tegra_init_cache(void)
 	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
 	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
 	writel(7, p + L2X0_PREFETCH_OFFSET);
+	writel(2, p + L2X0_PWR_CTRL);
 
 	l2x0_init(p, 0x7C480001, 0x8200c3fe);
 #endif