From: Dan Gohman <gohman@apple.com>
Date: Tue, 16 Dec 2008 03:31:11 +0000 (+0000)
Subject: Remove some special-case logic in ScheduleDAGSDNodes's
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9a65d6afc203fb8e44a807f84e3d370f16b08a5a;p=oota-llvm.git

Remove some special-case logic in ScheduleDAGSDNodes's
latency computation code that is no longer needed with the
new method for handling latencies.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61074 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 21df142ff34..08d6702fc81 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -196,12 +196,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
   
   // Compute the latency for the node.  We use the sum of the latencies for
   // all nodes flagged together into this SUnit.
-  if (InstrItins.isEmpty()) {
-    // No latency information.
-    SU->Latency = 1;
-    return;
-  }
-
   SU->Latency = 0;
   bool SawMachineOpcode = false;
   for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
@@ -210,10 +204,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
       SU->Latency +=
         InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
     }
-
-  // Ensure that CopyToReg and similar nodes have a non-zero latency.
-  if (!SawMachineOpcode)
-    SU->Latency = 1;
 }
 
 /// CountResults - The results of target nodes have register or immediate