From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 14 Feb 2015 02:55:56 +0000 (+0000)
Subject: R600/SI: Fix copies from SGPR to VCC
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9b6d620f89a4782d1c6ebceafb5b9e0e3369d2c7;p=oota-llvm.git

R600/SI: Fix copies from SGPR to VCC

This shows up without optimizations when vcc is required
to be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229226 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index 13775b5ec31..8b65d5ca6a9 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -333,12 +333,17 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
     if (DestReg == AMDGPU::VCC) {
-      // FIXME: Hack until VReg_1 removed.
+      if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
+        BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
+          .addReg(SrcReg, getKillRegState(KillSrc));
+      } else {
+        // FIXME: Hack until VReg_1 removed.
+        assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
+        BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
+          .addImm(0)
+          .addReg(SrcReg, getKillRegState(KillSrc));
+      }
 
-      assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
-      BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
-        .addImm(0)
-        .addReg(SrcReg, getKillRegState(KillSrc));
       return;
     }