From: Greg Meiste <w30289@motorola.com>
Date: Thu, 30 Sep 2010 16:40:22 +0000 (-0500)
Subject: spi: tegra: Increase delay between CS and clock start
X-Git-Tag: firefly_0821_release~9833^2~157^2~13
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9cd8acf1b9971bf049abab2fb8513fb6a2cd1a3b;p=firefly-linux-kernel-4.4.55.git

spi: tegra: Increase delay between CS and clock start

Some SPI devices require a delay between the CS and when the clock
starts.  Increase SS_SETUP to accommodate these devices.

Change-Id: I301e3583e70c722cadde5a9f91119881805dd3a5
Signed-off-by: Greg Meiste <w30289@motorola.com>
---

diff --git a/drivers/spi/spi_tegra.c b/drivers/spi/spi_tegra.c
index 6023da9a103a..3709d5dccd76 100644
--- a/drivers/spi/spi_tegra.c
+++ b/drivers/spi/spi_tegra.c
@@ -274,6 +274,7 @@ static void spi_tegra_start_transfer(struct spi_device *spi,
 		val |= SLINK_TXEN;
 	val |= SLINK_SS_EN_CS(spi->chip_select);
 	val |= SLINK_SPIE;
+	val |= SLINK_SS_SETUP(3);
 	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
 
 	val = spi_tegra_readl(tspi, SLINK_COMMAND);