From: libing <libing@rock-chips.com>
Date: Wed, 30 Apr 2014 09:28:18 +0000 (+0800)
Subject: rk3288 mipi dsi: add rockchip_mipidsi_lcd.txt and rockchip_mipidsi.txt，in Documentati...
X-Git-Tag: firefly_0821_release~5395
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9e41b24fe68026d2b14fa03e6e742665dd6792ff;p=firefly-linux-kernel-4.4.55.git
rk3288 mipi dsi: add rockchip_mipidsi_lcd.txt and rockchip_mipidsi.txt，in Documentation/devicetree/bindings/video/
---
diff --git a/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt b/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt
new file mode 100755
index 000000000000..bf571279392e
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/rockchip_mipidsi.txt
@@ -0,0 +1,39 @@
+Device-Tree bindings for rockchip mipi dsi driver
+
+Required properties:
+- compatible: value should be "rockchip,rk32-dsi".
+- rockchip,prop: dsi number.
+- reg: physical base address of the hdmi and length of memory mapped
+ region.
+- interrupts: interrupt number to the cpu.
+
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+- clocks-names: list of clock names sorted in the same order as the clocks
+ property. Must contain "pclk_hdmi" and "hdcp_clk_hdmi".
+- status: the dsi host status;
+ <disabled>: open the dsi host;
+ <okay>:close the dsi host;
+
+Example:
+
+ dsihost0: mipi@ff960000{
+ compatible = "rockchip,rk32-dsi";
+ rockchip,prop = <0>;
+ reg = <0xff960000 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
+ status = "okay";
+ };
+
+ dsihost1: mipi@ff964000{
+ compatible = "rockchip,rk32-dsi";
+ rockchip,prop = <1>;
+ reg = <0xff964000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
+ clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
+ status = "okay";
+ };
+
diff --git a/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt b/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt
new file mode 100755
index 000000000000..837a3bd76b7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/rockchip_mipidsi_lcd.txt
@@ -0,0 +1,173 @@
+Device-Tree bindings for rockchip mipi dsi lcd driver
+
+Required properties:
+ - rockchip,screen_init: Whether you need this screen initialization.
+ <0>: Don't need to be initialized.
+ <1>: Do need to be initialized.
+
+ - rockchip,dsi_lane: mipi lcd data lane number.
+
+ - rockchip,dsi_hs_clk: mipi lcd high speed clock.
+
+ - rockchip,mipi_dsi_num: mipi lcd dsi number.
+
+ - mipi_lcd_rst:mipi_lcd_rst: Should specify pin control groups used for reset this lcd.
+
+ - mipi_lcd_en:mipi_lcd_en: Should specify pin control groups used for enable this lcd.
+
+ - rockchip,gpios: gpio pin
+
+ - rockchip,delay: delay the millisecond.
+
+ - rockchip,cmd_debug : debug the cammands.
+ <0>: close the debug;
+ <1>: open the debug;
+
+ - rockchip,on-cmds1: write cammand to mipi lcd.
+
+- rockchip,cmd_type:
+ <LPDT>: close the debug;
+ <HSDT>: open the debug;
+
+ - rockchip,dsi_id: write cammand to mipi lcd(left and right).
+ <0>: left dsi;
+ <1>: right dsi;
+ <2>: left and right dsis;
+
+ - rockchip,cmd: cammand context.
+ The first parameter was data type;
+ The second parameter was index(register);
+ The third and ... parameter are cammand context;
+
+ - rockchip,cmd_delay: delay the millisecond.
+
+ - screen-type: mipi lcd type.
+ <SCREEN_DUAL_MIPI>: Dual channel mipi lcd.
+ <SCREEN_MIPI>: single channel mipi lcd.
+
+ - lvds-format:No relationship.
+
+ - out-face: DPI color coding as follows:
+ <OUT_P888>:24bit
+ <OUT_P666>:18bit
+ <OUT_P565>:16bit
+
+ - hactive, vactive: display resolution
+ - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
+ in pixels
+ vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
+ lines
+ - clock-frequency: display clock in Hz
+
+ - swap-rb :exchange of red and blue.
+ - swap-rg :exchange of red and green.
+ - swap-gb :exchange of green and blue.
+
+ - hsync-active: hsync pulse is active low/high/ignored
+ - vsync-active: vsync pulse is active low/high/ignored
+ - de-active: data-enable pulse is active low/high/ignored
+ - pixelclk-active: with
+ - active high = drive pixel data on rising edge/
+ sample data on falling edge
+ - active low = drive pixel data on falling edge/
+ sample data on rising edge
+ - ignored = ignored
+ - interlaced (bool): boolean to enable interlaced mode
+ - doublescan (bool): boolean to enable doublescan mode
+
+All the optional properties that are not bool follow the following logic:
+ <1>: high active
+ <0>: low active
+ omitted: not used on hardware
+
+There are different ways of describing the capabilities of a display. The
+devicetree representation corresponds to the one commonly found in datasheets
+for displays. If a display supports multiple signal timings, the native-mode
+can be specified.
+
+The parameters are defined as:
+
+ +----------+-------------------------------------+----------+-------+
+ | | ª | | |
+ | | |vback_porch | | |
+ | | « | | |
+ +----------#######################################----------+-------+
+ | # ª # | |
+ | # | # | |
+ | hback # | # hfront | hsync |
+ | porch # | hactive # porch | len |
+ |<-------->#<-------+--------------------------->#<-------->|<----->|
+ | # | # | |
+ | # |vactive # | |
+ | # | # | |
+ | # « # | |
+ +----------#######################################----------+-------+
+ | | ª | | |
+ | | |vfront_porch | | |
+ | | « | | |
+ +----------+-------------------------------------+----------+-------+
+ | | ª | | |
+ | | |vsync_len | | |
+ | | « | | |
+ +----------+-------------------------------------+----------+-------+
+
+
+Example:
+
+{
+ /* about mipi */
+ disp_mipi_init: mipi_dsi_init{
+ rockchip,screen_init = <1>;
+ rockchip,dsi_lane = <4>;
+ rockchip,dsi_hs_clk = <1020>;
+ rockchip,mipi_dsi_num = <2>;
+ };
+ disp_mipi_power_ctr: mipi_power_ctr {
+ mipi_lcd_rst:mipi_lcd_rst{
+ rockchip,gpios = <&gpio7 GPIO_B2 GPIO_ACTIVE_HIGH>;
+ rockchip,delay = <10>;
+ };
+ /*mipi_lcd_en:mipi_lcd_en {
+ rockchip,gpios = <&gpio6 GPIO_A7 GPIO_ACTIVE_HIGH>;
+ rockchip,delay = <10>;
+ };*/
+ };
+ disp_mipi_init_cmds: screen-on-cmds {
+ rockchip,cmd_debug = <0>;
+ rockchip,on-cmds1 {
+ rockchip,cmd_type = <LPDT>;
+ rockchip,dsi_id = <2>;
+ rockchip,cmd = <0x05 0x01>; //set soft reset
+ rockchip,cmd_delay = <10>;
+ };
+ };
+
+ disp_timings: display-timings {
+ native-mode = <&timing0>;
+ timing0: timing0 {
+ screen-type = <SCREEN_DUAL_MIPI>;
+ lvds-format = <LVDS_8BIT_2>;
+ out-face = <OUT_P888>;
+ clock-frequency = <285000000>;
+ hactive = <2560>;
+ vactive = <1600>;
+
+ hsync-len = <38>;//19
+ hback-porch = <80>;//40
+ hfront-porch = <246>;//123
+
+ vsync-len = <4>;
+ vback-porch = <4>;
+ vfront-porch = <12>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <0>;
+ pixelclk-active = <0>;
+ swap-rb = <0>;
+ swap-rg = <0>;
+ swap-gb = <0>;
+ };
+ };
+};
+