From: dkl <dkl@rock-chips.com>
Date: Tue, 1 Apr 2014 01:28:10 +0000 (+0800)
Subject: clk: rockchip: rk3288: not use usbphy_480m temporarily
X-Git-Tag: firefly_0821_release~5691
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9e47e4ddf4d37ebf8ef18aa265fba98448afe4c0;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: rk3288: not use usbphy_480m temporarily
---

diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi
index 506043697b88..8f36c83f9e05 100755
--- a/arch/arm/boot/dts/rk3288-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3288-clocks.dtsi
@@ -59,6 +59,13 @@
 				#clock-cells = <0>;
 			};
 
+			dummy_480m: dummy_480m {
+				compatible = "rockchip,rk-fixed-clock";
+				clock-output-names = "dummy_480m";
+				clock-frequency = <0>;
+				#clock-cells = <0>;
+			};
+
 			i2s_clkin: i2s_clkin {
 				compatible = "rockchip,rk-fixed-clock";
 				clock-output-names = "i2s_clkin";
@@ -839,7 +846,7 @@
 					clk_uart0_pll: clk_uart0_pll_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <13 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
 						clock-output-names = "clk_uart0_pll";
 						#clock-cells = <0>;
 					};
@@ -1433,7 +1440,7 @@
 					aclk_rga: aclk_rga_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <6 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "aclk_rga";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1455,7 +1462,7 @@
 					clk_rga: clk_rga_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <14 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "clk_rga";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1484,7 +1491,7 @@
 					aclk_vio0: aclk_vio0_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <6 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "aclk_vio0";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1506,7 +1513,7 @@
 					aclk_vio1: aclk_vio1_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <14 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "aclk_vio1";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1535,7 +1542,7 @@
 					clk_vepu: clk_vepu_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <6 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "clk_vepu";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1557,7 +1564,7 @@
 					clk_vdpu: clk_vdpu_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <14 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
 						clock-output-names = "clk_vdpu";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;
@@ -1617,7 +1624,7 @@
 					clk_gpu: clk_gpu_mux {
 						compatible = "rockchip,rk3188-mux-con";
 						rockchip,bits = <6 2>;
-						clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
+						clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
 						clock-output-names = "clk_gpu";
 						#clock-cells = <0>;
 						#clock-init-cells = <1>;