From: dkl <dkl@rock-chips.com>
Date: Wed, 28 May 2014 07:02:42 +0000 (+0800)
Subject: clk: rockchip: add rk3188plus_pll_com_table and some marcos, to
X-Git-Tag: firefly_0821_release~5210
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9f004277efb488a7e9679a148fb66ad02a928f33;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: add rk3188plus_pll_com_table and some marcos, to
separate CLK_PLL_3188PLUS pll type from CLK_PLL_3188 better.
---

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 7a1b76ce6cb1..56005494fd33 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -6,7 +6,7 @@
 #include "clk-pll.h"
 
 
-static const struct pll_clk_set pll_com_table[] = {
+static const struct pll_clk_set rk3188_pll_com_table[] = {
 	_RK3188_PLL_SET_CLKS(1250000,	12,	625,	1),
 	_RK3188_PLL_SET_CLKS(1200000,	1,	50,	1),
 	_RK3188_PLL_SET_CLKS(1188000,	2,	99,	1),
@@ -24,6 +24,24 @@ static const struct pll_clk_set pll_com_table[] = {
 	_RK3188_PLL_SET_CLKS(0,		0,	0,	0),
 };
 
+static const struct pll_clk_set rk3188plus_pll_com_table[] = {
+	_RK3188PLUS_PLL_SET_CLKS(1250000,	12,	625,	1),
+	_RK3188PLUS_PLL_SET_CLKS(1200000,	1,	50,	1),
+	_RK3188PLUS_PLL_SET_CLKS(1188000,	2,	99,	1),
+	_RK3188PLUS_PLL_SET_CLKS(891000,	8,	594,	2),
+	_RK3188PLUS_PLL_SET_CLKS(768000,	1,	64,	2),
+	_RK3188PLUS_PLL_SET_CLKS(594000,	2,	198,	4),
+	_RK3188PLUS_PLL_SET_CLKS(500000,	3,	250,	4),
+	_RK3188PLUS_PLL_SET_CLKS(408000,	1,	68,	4),
+	_RK3188PLUS_PLL_SET_CLKS(396000,	1,	66,	4),
+	_RK3188PLUS_PLL_SET_CLKS(384000,	2,	128,	4),
+	_RK3188PLUS_PLL_SET_CLKS(360000,	1,	60,	4),
+	_RK3188PLUS_PLL_SET_CLKS(300000,	1,	50,	4),
+	_RK3188PLUS_PLL_SET_CLKS(297000,	2,	198,	8),
+	_RK3188PLUS_PLL_SET_CLKS(148500,	2,	99,	8),
+	_RK3188PLUS_PLL_SET_CLKS(0,		0,	0,	0),
+};
+
 static const struct apll_clk_set rk3188_apll_table[] = {
 	//            (_mhz,	nr,	nf,	no,	_periph_div,	_aclk_div)
 	_RK3188_APLL_SET_CLKS(2208, 	1, 	92,	1, 	8,	81),
@@ -265,7 +283,7 @@ static long clk_pll_round_rate_3188(struct clk_hw *hw, unsigned long rate,
 		return rate;
 	}
 
-	return (pll_com_get_best_set(rate, pll_com_table)->rate);
+	return (pll_com_get_best_set(rate, rk3188_pll_com_table)->rate);
 }
 
 static int _pll_clk_set_rate_3188(struct pll_clk_set *clk_set,
@@ -321,7 +339,7 @@ static int clk_pll_set_rate_3188(struct clk_hw *hw, unsigned long rate,
 		unsigned long parent_rate)
 {
 	struct clk_pll *pll = to_clk_pll(hw);
-	struct pll_clk_set *clk_set = (struct pll_clk_set *)(pll_com_table);
+	struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188_pll_com_table);
 	int ret = 0;
 
 
@@ -600,7 +618,15 @@ static unsigned long clk_pll_recalc_rate_3188plus(struct clk_hw *hw,
 static long clk_pll_round_rate_3188plus(struct clk_hw *hw, unsigned long rate,
 		unsigned long *prate)
 {
-	return clk_pll_round_rate_3188(hw, rate, prate);
+	struct clk *parent = __clk_get_parent(hw->clk);
+
+	if (parent && (rate==__clk_get_rate(parent))) {
+		clk_debug("pll %s round rate=%lu equal to parent rate\n",
+				__clk_get_name(hw->clk), rate);
+		return rate;
+	}
+
+	return (pll_com_get_best_set(rate, rk3188plus_pll_com_table)->rate);
 }
 
 static int _pll_clk_set_rate_3188plus(struct pll_clk_set *clk_set,
@@ -656,7 +682,7 @@ static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
 		unsigned long parent_rate)
 {
 	//struct clk_pll *pll = to_clk_pll(hw);
-	struct pll_clk_set *clk_set = (struct pll_clk_set *)(pll_com_table);
+	struct pll_clk_set *clk_set = (struct pll_clk_set *)(rk3188plus_pll_com_table);
 	int ret = 0;
 
 #if 0
@@ -865,10 +891,10 @@ static int clk_pll_set_rate_3188plus_auto(struct clk_hw *hw, unsigned long rate,
 
 	/* prepare clk_set */
 	clk_set.rate = best;
-	clk_set.pllcon0 = RK3188_PLL_CLKR_SET(nr)|RK3188_PLL_CLKOD_SET(no), \
-	clk_set.pllcon1 = RK3188_PLL_CLKF_SET(nf),\
-	clk_set.pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
-	clk_set.rst_dly = ((nr*500)/24+1),\
+	clk_set.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no);
+	clk_set.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf);
+	clk_set.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1);
+	clk_set.rst_dly = ((nr*500)/24+1);
 
 	ret = _pll_clk_set_rate_3188plus(&clk_set, hw);
 	clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk), best);
diff --git a/drivers/clk/rockchip/clk-pll.h b/drivers/clk/rockchip/clk-pll.h
index a2828eca0d94..b985be91d0e3 100644
--- a/drivers/clk/rockchip/clk-pll.h
+++ b/drivers/clk/rockchip/clk-pll.h
@@ -91,15 +91,17 @@
 #define RK3188_PLL_NR(reg)		RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK)
 #define RK3188_PLL_CLKR_SET(val)	(RK3188_PLL_CLKR(val) | CRU_W_MSK(RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK))
 
-/*FIXME*/
 #define RK3188PLUS_PLL_OD_MSK		(0xf)
-#define RK3188PLUS_PLL_NO(reg)		(RK3188_PLL_NO(reg) & RK3188PLUS_PLL_OD_MSK)
+#define RK3188PLUS_PLL_OD_SHIFT 	(0x0)
+#define RK3188PLUS_PLL_CLKOD(val)	RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK)
+#define RK3188PLUS_PLL_NO(reg)		RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK)
+#define RK3188PLUS_PLL_CLKOD_SET(val)	(RK3188PLUS_PLL_CLKOD(val) | CRU_W_MSK(RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK))
 
 #define RK3188PLUS_PLL_NR_MSK		(0x3f)
-#define RK3188PLUS_PLL_NR(reg)		(RK3188_PLL_NR(reg) & RK3188PLUS_PLL_NR_MSK)
-
-#define RK3188PLUS_PLL_CLKR_SET(val)	RK3188_PLL_CLKR_SET(val & RK3188PLUS_PLL_NR_MSK)
-#define RK3188PLUS_PLL_CLKOD_SET(val)	RK3188_PLL_CLKOD_SET(val & RK3188PLUS_PLL_OD_MSK)
+#define RK3188PLUS_PLL_NR_SHIFT		(8)
+#define RK3188PLUS_PLL_CLKR(val)	RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK)
+#define RK3188PLUS_PLL_NR(reg)		RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK)
+#define RK3188PLUS_PLL_CLKR_SET(val)	(RK3188PLUS_PLL_CLKR(val) | CRU_W_MSK(RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK))
 
 /*******************PLL CON1 BITS***************************/
 #define RK3188_PLL_NF_MSK		(0xffff)
@@ -109,14 +111,20 @@
 #define RK3188_PLL_CLKF_SET(val)	(RK3188_PLL_CLKF(val) | CRU_W_MSK(RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK))
 
 #define RK3188PLUS_PLL_NF_MSK		(0x1fff)
-#define RK3188PLUS_PLL_NF(reg)		(RK3188_PLL_NF(reg) & RK3188PLUS_PLL_NF_MSK)
-#define RK3188PLUS_PLL_CLKF_SET(val)	RK3188_PLL_CLKF_SET(val & RK3188PLUS_PLL_NF_MSK)
+#define RK3188PLUS_PLL_NF_SHIFT		(0)
+#define RK3188PLUS_PLL_CLKF(val)	RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK)
+#define RK3188PLUS_PLL_NF(reg)		RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK)
+#define RK3188PLUS_PLL_CLKF_SET(val)	(RK3188PLUS_PLL_CLKF(val) | CRU_W_MSK(RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK))
 
 /*******************PLL CON2 BITS***************************/
 #define RK3188_PLL_BWADJ_MSK		(0xfff)
 #define RK3188_PLL_BWADJ_SHIFT		(0)
 #define RK3188_PLL_CLK_BWADJ_SET(val)	((val) | CRU_W_MSK(RK3188_PLL_BWADJ_SHIFT, RK3188_PLL_BWADJ_MSK))
 
+#define RK3188PLUS_PLL_BWADJ_MSK	(0xfff)
+#define RK3188PLUS_PLL_BWADJ_SHIFT	(0)
+#define RK3188PLUS_PLL_CLK_BWADJ_SET(val)	((val) | CRU_W_MSK(RK3188PLUS_PLL_BWADJ_SHIFT, RK3188PLUS_PLL_BWADJ_MSK))
+
 /*******************PLL CON3 BITS***************************/
 #define RK3188_PLL_RESET_MSK		(1 << 5)
 #define RK3188_PLL_RESET_W_MSK		(RK3188_PLL_RESET_MSK << 16)
@@ -177,6 +185,15 @@
 	.rst_dly = ((nr*500)/24+1),\
 }
 
+#define _RK3188PLUS_PLL_SET_CLKS(_mhz, nr, nf, no) \
+{ \
+	.rate   = (_mhz) * KHZ, \
+	.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no), \
+	.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
+	.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1),\
+	.rst_dly = ((nr*500)/24+1),\
+}
+
 #define _RK3188_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _aclk_div) \
 { \
 	.rate   = _mhz * MHZ, \
@@ -189,6 +206,7 @@
 	.lpj = (CLK_LOOPS_JIFFY_REF*_mhz) / CLK_LOOPS_RATE_REF,\
 }
 
+
 /*******************RK3288 PLL***********************************/
 /*******************CLKSEL0 BITS***************************/
 #define RK3288_CORE_SEL_PLL_W_MSK	(1 << 31)
@@ -230,9 +248,9 @@
 #define _RK3288_APLL_SET_CLKS(_mhz, nr, nf, no, l2_div, m0_div, mp_div, atclk_div, pclk_dbg_div) \
 { \
 	.rate   = _mhz * MHZ, \
-	.pllcon0 = RK3188_PLL_CLKR_SET(nr) | RK3188_PLL_CLKOD_SET(no), \
-	.pllcon1 = RK3188_PLL_CLKF_SET(nf),\
-	.pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
+	.pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr) | RK3188PLUS_PLL_CLKOD_SET(no), \
+	.pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
+	.pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1),\
 	.rst_dly = ((nr*500)/24+1),\
 	.clksel0 = RK3288_ACLK_M0_DIV(m0_div) | RK3288_ACLK_MP_DIV(mp_div),\
 	.clksel1 = RK3288_CLK_L2RAM_DIV(l2_div) | RK3288_ATCLK_DIV(atclk_div) | RK3288_PCLK_DBG_DIV(pclk_dbg_div),\