From: Tom Stellard Date: Fri, 28 Feb 2014 21:36:37 +0000 (+0000) Subject: R600/SI: Expand all v16[if]32 operations X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9f0d68f522ca0240b8e3dddb89e3e78099e1141e;p=oota-llvm.git R600/SI: Expand all v16[if]32 operations git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202543 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index e1256415309..b64e2deb19d 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -150,7 +150,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : // We only support LOAD/STORE and vector manipulation ops for vectors // with > 4 elements. MVT VecTypes[] = { - MVT::v8i32, MVT::v8f32 + MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32 }; const size_t NumVecTypes = array_lengthof(VecTypes); diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll index 8de87f4999f..600419cd167 100644 --- a/test/CodeGen/R600/add.ll +++ b/test/CodeGen/R600/add.ll @@ -76,6 +76,46 @@ entry: ret void } +; FUNC-LABEL: @test16 +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; EG-CHECK: ADD_INT +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +; SI-CHECK: S_ADD_I32 +define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { +entry: + %0 = add <16 x i32> %a, %b + store <16 x i32> %0, <16 x i32> addrspace(1)* %out + ret void +} + ; FUNC-LABEL: @add64 ; SI-CHECK: S_ADD_I32 ; SI-CHECK: S_ADDC_U32