From: Kevin Enderby Date: Tue, 20 Mar 2012 17:41:51 +0000 (+0000) Subject: Fix assembling ARM vst2 instructions with double-spaced registers. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=9f2e160f7ae90a7a80b17e38ad06f2c706515115;p=oota-llvm.git Fix assembling ARM vst2 instructions with double-spaced registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ccdadd81669..911eb132e56 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1102,7 +1102,7 @@ public: } bool isVecListDPairSpaced() const { - if (!isSingleSpacedVectorList()) return false; + if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s index 2b14d37a5b8..1f07461d10c 100644 --- a/test/MC/ARM/neon-vst-encoding.s +++ b/test/MC/ARM/neon-vst-encoding.s @@ -264,3 +264,7 @@ @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4] @ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4] diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s index 1722f12a00f..b50d8b63c1c 100644 --- a/test/MC/ARM/neont2-vst-encoding.s +++ b/test/MC/ARM/neont2-vst-encoding.s @@ -101,3 +101,7 @@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +@ rdar://11082188 + vst2.8 {d8, d10}, [r4] +@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x04,0xf9,0x0f,0x89]