From: Logan Chien <tzuhsiang.chien@gmail.com>
Date: Tue, 16 Apr 2013 14:02:30 +0000 (+0000)
Subject: Fix build failure introduced in 179591 when assertions are disabled.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a363b117f41700da0200753e6df62b5e2cb38378;p=oota-llvm.git

Fix build failure introduced in 179591 when assertions are disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179593 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index f17dcdf6ab2..52d92375aaf 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -428,7 +428,9 @@ void ARMELFStreamer::EmitSetFP(unsigned NewFPReg,
   const MCRegisterInfo &MRI = getContext().getRegisterInfo();
 
   uint16_t NewFPRegEncVal = MRI.getEncodingValue(NewFPReg);
+#ifndef NDEBUG
   uint16_t NewSPRegEncVal = MRI.getEncodingValue(NewSPReg);
+#endif
 
   assert((NewSPReg == ARM::SP || NewSPRegEncVal == FPReg) &&
          "the operand of .setfp directive should be either $sp or $fp");
@@ -446,7 +448,9 @@ void ARMELFStreamer::EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
                                  bool IsVector) {
   const MCRegisterInfo &MRI = getContext().getRegisterInfo();
 
+#ifndef NDEBUG
   unsigned Max = IsVector ? 32 : 16;
+#endif
   uint32_t &RegMask = IsVector ? VFPRegSave : RegSave;
 
   for (size_t i = 0; i < RegList.size(); ++i) {