From: Colin LeMahieu <colinl@codeaurora.org>
Date: Fri, 26 Dec 2014 19:12:11 +0000 (+0000)
Subject: [Hexagon] Adding post-increment unsigned byte loads.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a46bee194da18be9c408633e0c6f9e0311ec2dab;p=oota-llvm.git

[Hexagon] Adding post-increment unsigned byte loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224867 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index cf461a1d1b4..ab8e20ef21c 100644
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
       Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
   } else if (LoadedVT == MVT::i8) {
     if (TII->isValidAutoIncImm(LoadedVT, Val))
-      Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi;
+      Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
     else
       Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
   } else
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 71c92a5e8b4..f74c0231104 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -695,7 +695,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
 
   case Hexagon::L2_loadrb_pi:
-  case Hexagon::POST_LDriub:
+  case Hexagon::L2_loadrub_pi:
     return isInt<4>(MI->getOperand(3).getImm());
 
   case Hexagon::STrib_imm_V4:
@@ -1367,8 +1367,8 @@ isConditionalLoad (const MachineInstr* MI) const {
     case Hexagon::L2_ploadrbf_pi :
     case Hexagon::POST_LDriuh_cPt :
     case Hexagon::POST_LDriuh_cNotPt :
-    case Hexagon::POST_LDriub_cPt :
-    case Hexagon::POST_LDriub_cNotPt :
+    case Hexagon::L2_ploadrubt_pi :
+    case Hexagon::L2_ploadrubf_pi :
       return QRI.Subtarget.hasV4TOps();
     case Hexagon::LDrid_indexed_shl_cPt_V4 :
     case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index 6070a1fd076..172a5aff1ca 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -1698,6 +1698,7 @@ multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC,
 // post increment byte loads with immediate offset
 let accessSize = ByteAccess, isCodeGenOnly = 0 in {
   defm loadrb  : LD_PostInc <"memb",  "LDrib", IntRegs, s4_0Imm, 0b1000>;
+  defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
 }
 
 multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
@@ -1740,8 +1741,6 @@ multiclass LD_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
 }
 
 let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
-  defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>,
-                    PredNewRel;
   defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>,
                     PredNewRel;
   defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>,
diff --git a/test/MC/Disassembler/Hexagon/ld.txt b/test/MC/Disassembler/Hexagon/ld.txt
index c3d6556e59b..2c967fbe5c5 100644
--- a/test/MC/Disassembler/Hexagon/ld.txt
+++ b/test/MC/Disassembler/Hexagon/ld.txt
@@ -13,6 +13,8 @@
 
 0xf1 0xc3 0x15 0x91
 # CHECK: r17 = memb(r21 + #31)
+0xb1 0xc0 0x15 0x9b
+# CHECK: r17 = memb(r21++#5)
 0x91 0xdd 0x15 0x41
 # CHECK: if (p3) r17 = memb(r21 + #44)
 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
@@ -23,14 +25,24 @@
 0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
+0xb1 0xe6 0x15 0x9b
+# CHECK: if (p3) r17 = memb(r21++#5)
+0xb1 0xee 0x15 0x9b
+# CHECK: if (!p3) r17 = memb(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
 
 0xf1 0xc3 0x55 0x91
 # CHECK: r17 = memh(r21 + #62)
 
 0xf1 0xc3 0x35 0x91
 # CHECK: r17 = memub(r21 + #31)
-0xb1 0xc0 0x15 0x9b
-# CHECK: r17 = memb(r21++#5)
+0xb1 0xc0 0x35 0x9b
+# CHECK: r17 = memub(r21++#5)
 0xf1 0xdb 0x35 0x41
 # CHECK: if (p3) r17 = memub(r21 + #31)
 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
@@ -41,16 +53,16 @@
 0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
-0xb1 0xe6 0x15 0x9b
-# CHECK: if (p3) r17 = memb(r21++#5)
-0xb1 0xee 0x15 0x9b
-# CHECK: if (!p3) r17 = memb(r21++#5)
-0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b
+0xb1 0xe6 0x35 0x9b
+# CHECK: if (p3) r17 = memub(r21++#5)
+0xb1 0xee 0x35 0x9b
+# CHECK: if (!p3) r17 = memub(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xf6 0x35 0x9b
 # CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5)
-0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b
+# CHECK-NEXT: if (p3.new) r17 = memub(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xfe 0x35 0x9b
 # CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
+# CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
 
 0xb1 0xc2 0x75 0x91
 # CHECK: r17 = memuh(r21 + #42)