From: Evan Cheng <evan.cheng@apple.com>
Date: Wed, 13 Feb 2008 02:46:49 +0000 (+0000)
Subject: commuteInstr() can now commute non-ssa machine instrs.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a4d16a1f0dcdd1ab2862737105f900e2c577532d;p=oota-llvm.git

commuteInstr() can now commute non-ssa machine instrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index cd2bfcce023..598b94af9c4 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -23,8 +23,17 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
          "This only knows how to commute register operands so far");
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
+  MachineOperand &MO = MI->getOperand(0);
+  bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1;
   bool Reg1IsKill = MI->getOperand(1).isKill();
   bool Reg2IsKill = MI->getOperand(2).isKill();
+  if (UpdateReg0) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    Reg2IsKill = false;
+    MI->getOperand(0).setReg(Reg2);
+  }
   MI->getOperand(2).setReg(Reg1);
   MI->getOperand(1).setReg(Reg2);
   MI->getOperand(2).setIsKill(Reg1IsKill);
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 81c1003310b..bc4d4b9d515 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -147,10 +147,20 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
   //   Op0 = (Op2 & ~M) | (Op1 & M)
 
   // Swap op1/op2
+  unsigned Reg0 = MI->getOperand(0).getReg();
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
   bool Reg1IsKill = MI->getOperand(1).isKill();
   bool Reg2IsKill = MI->getOperand(2).isKill();
+  // If machine instrs are no longer in two-address forms, update
+  // destination register as well.
+  if (Reg0 == Reg1) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    MI->getOperand(0).setReg(Reg2);
+    Reg2IsKill = false;
+  }
   MI->getOperand(2).setReg(Reg1);
   MI->getOperand(1).setReg(Reg2);
   MI->getOperand(2).setIsKill(Reg1IsKill);
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 42c994a0a61..cfbce7e14d4 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1055,6 +1055,15 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
     unsigned C = MI->getOperand(2).getReg();
     bool BisKill = MI->getOperand(1).isKill();
     bool CisKill = MI->getOperand(2).isKill();
+    // If machine instrs are no longer in two-address forms, update
+    // destination register as well.
+    if (A == B) {
+      // Must be two address instruction!
+      assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+             "Expecting a two-address instruction!");
+      A = C;
+      CisKill = false;
+    }
     return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
       .addReg(B, false, false, BisKill).addImm(Size-Amt);
   }