From: Mark Brown Date: Thu, 15 May 2014 19:29:29 +0000 (+0100) Subject: Merge remote-tracking branch 'lsk/v3.10/topic/arm64-misc' into linux-linaro-lsk X-Git-Tag: firefly_0821_release~3680^2~127^2~3 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a5d53ad243dc3178fa9001d8ab1f19c63f8debd5;p=firefly-linux-kernel-4.4.55.git Merge remote-tracking branch 'lsk/v3.10/topic/arm64-misc' into linux-linaro-lsk Conflicts: Documentation/arm64/tagged-pointers.txt arch/arm64/Kconfig arch/arm64/boot/dts/Makefile arch/arm64/include/asm/arch_timer.h arch/arm64/include/asm/elf.h arch/arm64/include/asm/spinlock.h arch/arm64/kernel/smp.c --- a5d53ad243dc3178fa9001d8ab1f19c63f8debd5 diff --cc arch/arm64/Kconfig index 5ee96e17c63c,dba7308041ad..73366a635c3b --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@@ -9,11 -8,10 +9,12 @@@ config ARM6 select ARM_AMBA select ARM_ARCH_TIMER select ARM_GIC + select BUILDTIME_EXTABLE_SORT select CLONE_BACKWARDS select COMMON_CLK + select CPU_PM if (SUSPEND || CPU_IDLE) select GENERIC_CLOCKEVENTS + select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IOMAP select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW @@@ -270,15 -151,9 +272,16 @@@ config NR_CPU int "Maximum number of CPUs (2-32)" range 2 32 depends on SMP - default "4" + # These have to remain sorted largest to smallest + default "8" +config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs" + depends on SMP + help + Say Y here to experiment with turning CPUs off and on. CPUs + can be controlled through /sys/devices/system/cpu. + source kernel/Kconfig.preempt config HZ diff --cc arch/arm64/boot/dts/Makefile index 675be339c648,c52bdb051f66..ef388176116d --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@@ -1,6 -1,5 +1,7 @@@ -dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb \ + fvp-base-gicv2-psci.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb + dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb targets += dtbs targets += $(dtb-y) diff --cc arch/arm64/include/asm/elf.h index 212b0b615b4a,e7fa87f9201b..01d3aab64b79 --- a/arch/arm64/include/asm/elf.h +++ b/arch/arm64/include/asm/elf.h @@@ -164,13 -149,7 +162,12 @@@ extern unsigned long arch_randomize_brk #define arch_randomize_brk arch_randomize_brk #ifdef CONFIG_COMPAT - #define EM_ARM 40 + +#ifdef __AARCH64EB__ +#define COMPAT_ELF_PLATFORM ("v8b") +#else #define COMPAT_ELF_PLATFORM ("v8l") +#endif #define COMPAT_ELF_ET_DYN_BASE (randomize_et_dyn(2 * TASK_SIZE_32 / 3)) diff --cc arch/arm64/include/asm/hwcap.h index 3a48433dfb57,e2950b098e76..6cddbb0c9f54 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@@ -38,12 -37,12 +38,12 @@@ * instruction set this cpu supports. */ #define ELF_HWCAP (elf_hwcap) -#define COMPAT_ELF_HWCAP (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ - COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ - COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ - COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ - COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) + +#ifdef CONFIG_COMPAT +#define COMPAT_ELF_HWCAP (compat_elf_hwcap) +extern unsigned int compat_elf_hwcap; +#endif - extern unsigned int elf_hwcap; + extern unsigned long elf_hwcap; #endif #endif diff --cc arch/arm64/kernel/setup.c index 7b881f0a9cd1,40ae3ced37a1..8c7e81c0143f --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@@ -58,19 -57,9 +58,19 @@@ unsigned int processor_id; EXPORT_SYMBOL(processor_id); - unsigned int elf_hwcap __read_mostly; + unsigned long elf_hwcap __read_mostly; EXPORT_SYMBOL_GPL(elf_hwcap); +#ifdef CONFIG_COMPAT +#define COMPAT_ELF_HWCAP_DEFAULT \ + (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ + COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ + COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ + COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ + COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) +unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; +#endif + static const char *cpu_name; static const char *machine_name; phys_addr_t __fdt_pointer __initdata; diff --cc arch/arm64/kernel/smp.c index 4d101cbc0fee,97eaf79319d5..6b0001216189 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@@ -152,16 -187,18 +152,16 @@@ asmlinkage void __cpuinit secondary_sta preempt_disable(); trace_hardirqs_off(); - /* - * Let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(INVALID_HWID); + if (cpu_ops[cpu]->cpu_postboot) + cpu_ops[cpu]->cpu_postboot(); - smp_store_cpu_info(cpu); - /* - * Synchronise with the boot thread. + * Enable GIC and timers. */ - raw_spin_lock(&boot_lock); - raw_spin_unlock(&boot_lock); + notify_cpu_starting(cpu); + ++ smp_store_cpu_info(cpu); + /* * OK, now it's safe to let the boot CPU continue. Wait for * the CPU migration code to notice that the CPU is online @@@ -170,9 -207,14 +170,12 @@@ set_cpu_online(cpu, true); complete(&cpu_running); - /* - * Enable GIC and timers. - */ - notify_cpu_starting(cpu); + local_irq_enable(); + local_fiq_enable(); + local_irq_enable(); + local_fiq_enable(); + /* * OK, it's off to the idle thread for us */