From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 26 Sep 2008 19:14:21 +0000 (+0000)
Subject: Avoid spilling EBP / RBP twice in the prologue.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=a67f32abb5392981dbcb4de4e25bdedb046a8566;p=oota-llvm.git

Avoid spilling EBP / RBP twice in the prologue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56675 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 0864fa0b94c..c19628b81b5 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1832,39 +1832,49 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 }
 
 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                                MachineBasicBlock::iterator MI,
+                                             MachineBasicBlock::iterator MI,
                                 const std::vector<CalleeSavedInfo> &CSI) const {
   if (CSI.empty())
     return false;
 
-  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
-  unsigned SlotSize = is64Bit ? 8 : 4;
-
   MachineFunction &MF = *MBB.getParent();
-  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
-  X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
-  
+  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
+  unsigned FrameReg = is64Bit ? X86::RBP : X86::EBP;
   unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
+  unsigned CSSize = 0;
   for (unsigned i = CSI.size(); i != 0; --i) {
     unsigned Reg = CSI[i-1].getReg();
+    if (Reg == FrameReg && RI.hasFP(MF))
+      // It will be saved as part of the prologue.
+      continue;
     // Add the callee-saved register as live-in. It's killed at the spill.
     MBB.addLiveIn(Reg);
     BuildMI(MBB, MI, get(Opc)).addReg(Reg);
+    ++CSSize;
   }
+
+  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
+  unsigned SlotSize = is64Bit ? 8 : 4;
+  X86FI->setCalleeSavedFrameSize(CSSize * SlotSize);
   return true;
 }
 
 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                                 MachineBasicBlock::iterator MI,
+                                               MachineBasicBlock::iterator MI,
                                 const std::vector<CalleeSavedInfo> &CSI) const {
   if (CSI.empty())
     return false;
     
+  MachineFunction &MF = *MBB.getParent();
   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
+  unsigned FrameReg = is64Bit ? X86::RBP : X86::EBP;
 
   unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     unsigned Reg = CSI[i].getReg();
+    if (Reg == FrameReg && RI.hasFP(MF))
+      // It will be restored as part of the epilogue.
+      continue;
     BuildMI(MBB, MI, get(Opc), Reg);
   }
   return true;
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
index e22b647a13f..8aa330e7b1a 100644
--- a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
@@ -1,5 +1,5 @@
 ; Check that eh_return & unwind_init were properly lowered
-; RUN: llvm-as < %s | llc | grep %ebp | count 9
+; RUN: llvm-as < %s | llc | grep %ebp | count 7
 ; RUN: llvm-as < %s | llc | grep %ecx | count 5
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
index 7d01824400c..80eeba7e1ea 100644
--- a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
@@ -1,5 +1,5 @@
 ; Check that eh_return & unwind_init were properly lowered
-; RUN: llvm-as < %s | llc | grep %rbp | count 7
+; RUN: llvm-as < %s | llc | grep %rbp | count 5
 ; RUN: llvm-as < %s | llc | grep %rcx | count 3
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"